1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_SYS_GENERIC_BOARD 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* 14 * B4860 QDS board configuration file 15 */ 16 #define CONFIG_B4860QDS 17 #define CONFIG_PHYS_64BIT 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 21 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 22 #ifndef CONFIG_NAND 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #else 26 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 27 #define CONFIG_SPL_ENV_SUPPORT 28 #define CONFIG_SPL_SERIAL_SUPPORT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_SPL_LIBGENERIC_SUPPORT 32 #define CONFIG_SPL_LIBCOMMON_SUPPORT 33 #define CONFIG_SPL_I2C_SUPPORT 34 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 35 #define CONFIG_FSL_LAW /* Use common FSL init code */ 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 #define CONFIG_SPL_NAND_SUPPORT 43 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 44 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 48 #define CONFIG_SPL_NAND_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_SKIP_RELOCATE 51 #define CONFIG_SPL_COMMON_INIT_DDR 52 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 53 #define CONFIG_SYS_NO_FLASH 54 #endif 55 #endif 56 #endif 57 58 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 59 /* Set 1M boot space */ 60 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 61 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 62 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 63 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 /* High Level Configuration Options */ 68 #define CONFIG_BOOKE 69 #define CONFIG_E500 /* BOOKE e500 family */ 70 #define CONFIG_E500MC /* BOOKE e500mc family */ 71 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 72 #define CONFIG_MP /* support multiple processors */ 73 74 #ifndef CONFIG_SYS_TEXT_BASE 75 #define CONFIG_SYS_TEXT_BASE 0xeff40000 76 #endif 77 78 #ifndef CONFIG_RESET_VECTOR_ADDRESS 79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 80 #endif 81 82 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 83 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 84 #define CONFIG_FSL_IFC /* Enable IFC Support */ 85 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 86 #define CONFIG_PCI /* Enable PCI/PCIE */ 87 #define CONFIG_PCIE1 /* PCIE controler 1 */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 89 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 90 91 #ifndef CONFIG_PPC_B4420 92 #define CONFIG_SYS_SRIO 93 #define CONFIG_SRIO1 /* SRIO port 1 */ 94 #define CONFIG_SRIO2 /* SRIO port 2 */ 95 #define CONFIG_SRIO_PCIE_BOOT_MASTER 96 #endif 97 98 #define CONFIG_FSL_LAW /* Use common FSL init code */ 99 100 /* I2C bus multiplexer */ 101 #define I2C_MUX_PCA_ADDR 0x77 102 103 /* VSC Crossbar switches */ 104 #define CONFIG_VSC_CROSSBAR 105 #define I2C_CH_DEFAULT 0x8 106 #define I2C_CH_VSC3316 0xc 107 #define I2C_CH_VSC3308 0xd 108 109 #define VSC3316_TX_ADDRESS 0x70 110 #define VSC3316_RX_ADDRESS 0x71 111 #define VSC3308_TX_ADDRESS 0x02 112 #define VSC3308_RX_ADDRESS 0x03 113 114 /* IDT clock synthesizers */ 115 #define CONFIG_IDT8T49N222A 116 #define I2C_CH_IDT 0x9 117 118 #define IDT_SERDES1_ADDRESS 0x6E 119 #define IDT_SERDES2_ADDRESS 0x6C 120 121 /* Voltage monitor on channel 2*/ 122 #define I2C_MUX_CH_VOL_MONITOR 0xa 123 #define I2C_VOL_MONITOR_ADDR 0x40 124 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 125 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 126 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 127 128 #define CONFIG_ZM7300 129 #define I2C_MUX_CH_DPM 0xa 130 #define I2C_DPM_ADDR 0x28 131 132 #define CONFIG_ENV_OVERWRITE 133 134 #ifdef CONFIG_SYS_NO_FLASH 135 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 136 #define CONFIG_ENV_IS_NOWHERE 137 #endif 138 #else 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #endif 143 144 #if defined(CONFIG_SPIFLASH) 145 #define CONFIG_SYS_EXTRA_ENV_RELOC 146 #define CONFIG_ENV_IS_IN_SPI_FLASH 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 10000000 150 #define CONFIG_ENV_SPI_MODE 0 151 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 152 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 153 #define CONFIG_ENV_SECT_SIZE 0x10000 154 #elif defined(CONFIG_SDCARD) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_MMC 157 #define CONFIG_SYS_MMC_ENV_DEV 0 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (512 * 1097) 160 #elif defined(CONFIG_NAND) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_NAND 163 #define CONFIG_ENV_SIZE 0x2000 164 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 165 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 166 #define CONFIG_ENV_IS_IN_REMOTE 167 #define CONFIG_ENV_ADDR 0xffe20000 168 #define CONFIG_ENV_SIZE 0x2000 169 #elif defined(CONFIG_ENV_IS_NOWHERE) 170 #define CONFIG_ENV_SIZE 0x2000 171 #else 172 #define CONFIG_ENV_IS_IN_FLASH 173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 176 #endif 177 178 #ifndef __ASSEMBLY__ 179 unsigned long get_board_sys_clk(void); 180 unsigned long get_board_ddr_clk(void); 181 #endif 182 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 183 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 184 185 /* 186 * These can be toggled for performance analysis, otherwise use default. 187 */ 188 #define CONFIG_SYS_CACHE_STASHING 189 #define CONFIG_BTB /* toggle branch predition */ 190 #define CONFIG_DDR_ECC 191 #ifdef CONFIG_DDR_ECC 192 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 193 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 194 #endif 195 196 #define CONFIG_ENABLE_36BIT_PHYS 197 198 #ifdef CONFIG_PHYS_64BIT 199 #define CONFIG_ADDR_MAP 200 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 201 #endif 202 203 #if 0 204 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 205 #endif 206 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 207 #define CONFIG_SYS_MEMTEST_END 0x00400000 208 #define CONFIG_SYS_ALT_MEMTEST 209 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 210 211 /* 212 * Config the L3 Cache as L3 SRAM 213 */ 214 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 215 #define CONFIG_SYS_L3_SIZE 256 << 10 216 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 217 #ifdef CONFIG_NAND 218 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 219 #endif 220 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 221 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 222 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 223 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 224 225 #ifdef CONFIG_PHYS_64BIT 226 #define CONFIG_SYS_DCSRBAR 0xf0000000 227 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 228 #endif 229 230 /* EEPROM */ 231 #define CONFIG_ID_EEPROM 232 #define CONFIG_SYS_I2C_EEPROM_NXID 233 #define CONFIG_SYS_EEPROM_BUS_NUM 0 234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 238 239 /* 240 * DDR Setup 241 */ 242 #define CONFIG_VERY_BIG_RAM 243 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 244 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 245 246 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 247 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 248 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 249 250 #define CONFIG_DDR_SPD 251 #define CONFIG_SYS_DDR_RAW_TIMING 252 #define CONFIG_SYS_FSL_DDR3 253 #ifndef CONFIG_SPL_BUILD 254 #define CONFIG_FSL_DDR_INTERACTIVE 255 #endif 256 257 #define CONFIG_SYS_SPD_BUS_NUM 0 258 #define SPD_EEPROM_ADDRESS1 0x51 259 #define SPD_EEPROM_ADDRESS2 0x53 260 261 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 262 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 263 264 /* 265 * IFC Definitions 266 */ 267 #define CONFIG_SYS_FLASH_BASE 0xe0000000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 270 #else 271 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 272 #endif 273 274 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 275 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 276 + 0x8000000) | \ 277 CSPR_PORT_SIZE_16 | \ 278 CSPR_MSEL_NOR | \ 279 CSPR_V) 280 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 281 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 282 CSPR_PORT_SIZE_16 | \ 283 CSPR_MSEL_NOR | \ 284 CSPR_V) 285 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 286 /* NOR Flash Timing Params */ 287 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 288 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 289 FTIM0_NOR_TEADC(0x04) | \ 290 FTIM0_NOR_TEAHC(0x20)) 291 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 292 FTIM1_NOR_TRAD_NOR(0x1A) |\ 293 FTIM1_NOR_TSEQRAD_NOR(0x13)) 294 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 295 FTIM2_NOR_TCH(0x0E) | \ 296 FTIM2_NOR_TWPH(0x0E) | \ 297 FTIM2_NOR_TWP(0x1c)) 298 #define CONFIG_SYS_NOR_FTIM3 0x0 299 300 #define CONFIG_SYS_FLASH_QUIET_TEST 301 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 302 303 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 304 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 305 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 306 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 307 308 #define CONFIG_SYS_FLASH_EMPTY_INFO 309 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 310 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 311 312 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 313 #define CONFIG_FSL_QIXIS_V2 314 #define QIXIS_BASE 0xffdf0000 315 #ifdef CONFIG_PHYS_64BIT 316 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 317 #else 318 #define QIXIS_BASE_PHYS QIXIS_BASE 319 #endif 320 #define QIXIS_LBMAP_SWITCH 0x01 321 #define QIXIS_LBMAP_MASK 0x0f 322 #define QIXIS_LBMAP_SHIFT 0 323 #define QIXIS_LBMAP_DFLTBANK 0x00 324 #define QIXIS_LBMAP_ALTBANK 0x02 325 #define QIXIS_RST_CTL_RESET 0x31 326 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 327 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 328 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 329 330 #define CONFIG_SYS_CSPR3_EXT (0xf) 331 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 332 | CSPR_PORT_SIZE_8 \ 333 | CSPR_MSEL_GPCM \ 334 | CSPR_V) 335 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 336 #define CONFIG_SYS_CSOR3 0x0 337 /* QIXIS Timing parameters for IFC CS3 */ 338 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 339 FTIM0_GPCM_TEADC(0x0e) | \ 340 FTIM0_GPCM_TEAHC(0x0e)) 341 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 342 FTIM1_GPCM_TRAD(0x1f)) 343 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 344 FTIM2_GPCM_TCH(0x8) | \ 345 FTIM2_GPCM_TWP(0x1f)) 346 #define CONFIG_SYS_CS3_FTIM3 0x0 347 348 /* NAND Flash on IFC */ 349 #define CONFIG_NAND_FSL_IFC 350 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 351 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 352 #define CONFIG_SYS_NAND_BASE 0xff800000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 355 #else 356 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 357 #endif 358 359 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 360 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 362 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 363 | CSPR_V) 364 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 365 366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 369 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 370 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 371 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 372 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 373 374 #define CONFIG_SYS_NAND_ONFI_DETECTION 375 376 /* ONFI NAND Flash mode0 Timing Params */ 377 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 378 FTIM0_NAND_TWP(0x18) | \ 379 FTIM0_NAND_TWCHT(0x07) | \ 380 FTIM0_NAND_TWH(0x0a)) 381 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 382 FTIM1_NAND_TWBE(0x39) | \ 383 FTIM1_NAND_TRR(0x0e) | \ 384 FTIM1_NAND_TRP(0x18)) 385 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 386 FTIM2_NAND_TREH(0x0a) | \ 387 FTIM2_NAND_TWHRE(0x1e)) 388 #define CONFIG_SYS_NAND_FTIM3 0x0 389 390 #define CONFIG_SYS_NAND_DDR_LAW 11 391 392 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 393 #define CONFIG_SYS_MAX_NAND_DEVICE 1 394 #define CONFIG_MTD_NAND_VERIFY_WRITE 395 #define CONFIG_CMD_NAND 396 397 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 398 399 #if defined(CONFIG_NAND) 400 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 401 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 402 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 403 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 404 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 405 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 406 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 407 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 408 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 409 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 410 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 411 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 412 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 413 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 414 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 415 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 416 #else 417 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 418 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 419 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 420 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 421 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 422 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 423 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 424 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 425 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 426 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 427 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 428 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 429 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 430 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 431 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 432 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 433 #endif 434 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 435 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 436 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 437 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 438 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 439 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 440 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 441 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 442 443 #ifdef CONFIG_SPL_BUILD 444 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 445 #else 446 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 447 #endif 448 449 #if defined(CONFIG_RAMBOOT_PBL) 450 #define CONFIG_SYS_RAMBOOT 451 #endif 452 453 #define CONFIG_BOARD_EARLY_INIT_R 454 #define CONFIG_MISC_INIT_R 455 456 #define CONFIG_HWCONFIG 457 458 /* define to use L1 as initial stack */ 459 #define CONFIG_L1_INIT_RAM 460 #define CONFIG_SYS_INIT_RAM_LOCK 461 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 465 /* The assembler doesn't like typecast */ 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 467 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 468 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 469 #else 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 473 #endif 474 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 475 476 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 477 GENERATED_GBL_DATA_SIZE) 478 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 479 480 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 481 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 482 483 /* Serial Port - controlled on board with jumper J8 484 * open - index 2 485 * shorted - index 1 486 */ 487 #define CONFIG_CONS_INDEX 1 488 #define CONFIG_SYS_NS16550 489 #define CONFIG_SYS_NS16550_SERIAL 490 #define CONFIG_SYS_NS16550_REG_SIZE 1 491 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 492 493 #define CONFIG_SYS_BAUDRATE_TABLE \ 494 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 495 496 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 497 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 498 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 499 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 500 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 501 #ifndef CONFIG_SPL_BUILD 502 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 503 #endif 504 505 506 /* Use the HUSH parser */ 507 #define CONFIG_SYS_HUSH_PARSER 508 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 509 510 /* pass open firmware flat tree */ 511 #define CONFIG_OF_LIBFDT 512 #define CONFIG_OF_BOARD_SETUP 513 #define CONFIG_OF_STDOUT_VIA_ALIAS 514 515 /* new uImage format support */ 516 #define CONFIG_FIT 517 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 518 519 /* I2C */ 520 #define CONFIG_SYS_I2C 521 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 522 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 523 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 524 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 525 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 526 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 527 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 528 529 /* 530 * RTC configuration 531 */ 532 #define RTC 533 #define CONFIG_RTC_DS3231 1 534 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 535 536 /* 537 * RapidIO 538 */ 539 #ifdef CONFIG_SYS_SRIO 540 #ifdef CONFIG_SRIO1 541 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 542 #ifdef CONFIG_PHYS_64BIT 543 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 544 #else 545 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 546 #endif 547 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 548 #endif 549 550 #ifdef CONFIG_SRIO2 551 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 554 #else 555 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 556 #endif 557 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 558 #endif 559 #endif 560 561 /* 562 * for slave u-boot IMAGE instored in master memory space, 563 * PHYS must be aligned based on the SIZE 564 */ 565 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 566 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 567 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 568 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 569 /* 570 * for slave UCODE and ENV instored in master memory space, 571 * PHYS must be aligned based on the SIZE 572 */ 573 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 574 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 575 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 576 577 /* slave core release by master*/ 578 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 579 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 580 581 /* 582 * SRIO_PCIE_BOOT - SLAVE 583 */ 584 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 585 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 586 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 587 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 588 #endif 589 590 /* 591 * eSPI - Enhanced SPI 592 */ 593 #define CONFIG_FSL_ESPI 594 #define CONFIG_SPI_FLASH 595 #define CONFIG_SPI_FLASH_SST 596 #define CONFIG_CMD_SF 597 #define CONFIG_SF_DEFAULT_SPEED 10000000 598 #define CONFIG_SF_DEFAULT_MODE 0 599 600 /* 601 * MAPLE 602 */ 603 #ifdef CONFIG_PHYS_64BIT 604 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 605 #else 606 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 607 #endif 608 609 /* 610 * General PCI 611 * Memory space is mapped 1-1, but I/O space must start from 0. 612 */ 613 614 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 615 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 616 #ifdef CONFIG_PHYS_64BIT 617 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 618 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 619 #else 620 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 621 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 622 #endif 623 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 624 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 625 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 626 #ifdef CONFIG_PHYS_64BIT 627 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 628 #else 629 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 630 #endif 631 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 632 633 /* Qman/Bman */ 634 #ifndef CONFIG_NOBQFMAN 635 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 636 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 637 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 638 #ifdef CONFIG_PHYS_64BIT 639 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 640 #else 641 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 642 #endif 643 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 644 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 645 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 646 #ifdef CONFIG_PHYS_64BIT 647 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 648 #else 649 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 650 #endif 651 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 652 653 #define CONFIG_SYS_DPAA_FMAN 654 655 #define CONFIG_SYS_DPAA_RMAN 656 657 /* Default address of microcode for the Linux Fman driver */ 658 #if defined(CONFIG_SPIFLASH) 659 /* 660 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 661 * env, so we got 0x110000. 662 */ 663 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 664 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 665 #elif defined(CONFIG_SDCARD) 666 /* 667 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 668 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 669 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 670 */ 671 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 672 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 673 #elif defined(CONFIG_NAND) 674 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 675 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 676 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 677 /* 678 * Slave has no ucode locally, it can fetch this from remote. When implementing 679 * in two corenet boards, slave's ucode could be stored in master's memory 680 * space, the address can be mapped from slave TLB->slave LAW-> 681 * slave SRIO or PCIE outbound window->master inbound window-> 682 * master LAW->the ucode address in master's memory space. 683 */ 684 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 685 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 686 #else 687 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 688 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 689 #endif 690 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 691 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 692 #endif /* CONFIG_NOBQFMAN */ 693 694 #ifdef CONFIG_SYS_DPAA_FMAN 695 #define CONFIG_FMAN_ENET 696 #define CONFIG_PHYLIB_10G 697 #define CONFIG_PHY_VITESSE 698 #define CONFIG_PHY_TERANETICS 699 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 700 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 701 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 702 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 703 #endif 704 705 #ifdef CONFIG_PCI 706 #define CONFIG_PCI_INDIRECT_BRIDGE 707 #define CONFIG_NET_MULTI 708 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 709 #define CONFIG_E1000 710 711 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 712 #define CONFIG_DOS_PARTITION 713 #endif /* CONFIG_PCI */ 714 715 #ifdef CONFIG_FMAN_ENET 716 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 717 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 718 719 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 720 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 721 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 722 723 724 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 725 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 726 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 727 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 728 729 #define CONFIG_MII /* MII PHY management */ 730 #define CONFIG_ETHPRIME "FM1@DTSEC1" 731 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 732 #endif 733 734 /* 735 * Environment 736 */ 737 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 738 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 739 740 /* 741 * Command line configuration. 742 */ 743 #include <config_cmd_default.h> 744 745 #define CONFIG_CMD_DATE 746 #define CONFIG_CMD_DHCP 747 #define CONFIG_CMD_EEPROM 748 #define CONFIG_CMD_ELF 749 #define CONFIG_CMD_ERRATA 750 #define CONFIG_CMD_GREPENV 751 #define CONFIG_CMD_IRQ 752 #define CONFIG_CMD_I2C 753 #define CONFIG_CMD_MII 754 #define CONFIG_CMD_PING 755 #define CONFIG_CMD_REGINFO 756 #define CONFIG_CMD_SETEXPR 757 758 #ifdef CONFIG_PCI 759 #define CONFIG_CMD_PCI 760 #define CONFIG_CMD_NET 761 #endif 762 763 /* Hash command with SHA acceleration supported in hardware */ 764 #ifdef CONFIG_FSL_CAAM 765 #define CONFIG_CMD_HASH 766 #define CONFIG_SHA_HW_ACCEL 767 #endif 768 769 /* 770 * USB 771 */ 772 #define CONFIG_HAS_FSL_DR_USB 773 774 #ifdef CONFIG_HAS_FSL_DR_USB 775 #define CONFIG_USB_EHCI 776 777 #ifdef CONFIG_USB_EHCI 778 #define CONFIG_CMD_USB 779 #define CONFIG_USB_STORAGE 780 #define CONFIG_USB_EHCI_FSL 781 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 782 #define CONFIG_CMD_EXT2 783 #endif 784 #endif 785 786 /* 787 * Miscellaneous configurable options 788 */ 789 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 790 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 791 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 792 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 793 #ifdef CONFIG_CMD_KGDB 794 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 795 #else 796 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 797 #endif 798 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 799 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 800 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 801 802 /* 803 * For booting Linux, the board info and command line data 804 * have to be in the first 64 MB of memory, since this is 805 * the maximum mapped by the Linux kernel during initialization. 806 */ 807 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 808 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 809 810 #ifdef CONFIG_CMD_KGDB 811 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 812 #endif 813 814 /* 815 * Environment Configuration 816 */ 817 #define CONFIG_ROOTPATH "/opt/nfsroot" 818 #define CONFIG_BOOTFILE "uImage" 819 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 820 821 /* default location for tftp and bootm */ 822 #define CONFIG_LOADADDR 1000000 823 824 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 825 826 #define CONFIG_BAUDRATE 115200 827 828 #define __USB_PHY_TYPE ulpi 829 830 #ifdef CONFIG_PPC_B4860 831 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 832 "bank_intlv=cs0_cs1;" \ 833 "en_cpc:cpc2;" 834 #else 835 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 836 #endif 837 838 #define CONFIG_EXTRA_ENV_SETTINGS \ 839 HWCONFIG \ 840 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 841 "netdev=eth0\0" \ 842 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 843 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 844 "tftpflash=tftpboot $loadaddr $uboot && " \ 845 "protect off $ubootaddr +$filesize && " \ 846 "erase $ubootaddr +$filesize && " \ 847 "cp.b $loadaddr $ubootaddr $filesize && " \ 848 "protect on $ubootaddr +$filesize && " \ 849 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 850 "consoledev=ttyS0\0" \ 851 "ramdiskaddr=2000000\0" \ 852 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 853 "fdtaddr=c00000\0" \ 854 "fdtfile=b4860qds/b4860qds.dtb\0" \ 855 "bdev=sda3\0" 856 857 /* For emulation this causes u-boot to jump to the start of the proof point 858 app code automatically */ 859 #define CONFIG_PROOF_POINTS \ 860 "setenv bootargs root=/dev/$bdev rw " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "cpu 1 release 0x29000000 - - -;" \ 863 "cpu 2 release 0x29000000 - - -;" \ 864 "cpu 3 release 0x29000000 - - -;" \ 865 "cpu 4 release 0x29000000 - - -;" \ 866 "cpu 5 release 0x29000000 - - -;" \ 867 "cpu 6 release 0x29000000 - - -;" \ 868 "cpu 7 release 0x29000000 - - -;" \ 869 "go 0x29000000" 870 871 #define CONFIG_HVBOOT \ 872 "setenv bootargs config-addr=0x60000000; " \ 873 "bootm 0x01000000 - 0x00f00000" 874 875 #define CONFIG_ALU \ 876 "setenv bootargs root=/dev/$bdev rw " \ 877 "console=$consoledev,$baudrate $othbootargs;" \ 878 "cpu 1 release 0x01000000 - - -;" \ 879 "cpu 2 release 0x01000000 - - -;" \ 880 "cpu 3 release 0x01000000 - - -;" \ 881 "cpu 4 release 0x01000000 - - -;" \ 882 "cpu 5 release 0x01000000 - - -;" \ 883 "cpu 6 release 0x01000000 - - -;" \ 884 "cpu 7 release 0x01000000 - - -;" \ 885 "go 0x01000000" 886 887 #define CONFIG_LINUX \ 888 "setenv bootargs root=/dev/ram rw " \ 889 "console=$consoledev,$baudrate $othbootargs;" \ 890 "setenv ramdiskaddr 0x02000000;" \ 891 "setenv fdtaddr 0x00c00000;" \ 892 "setenv loadaddr 0x1000000;" \ 893 "bootm $loadaddr $ramdiskaddr $fdtaddr" 894 895 #define CONFIG_HDBOOT \ 896 "setenv bootargs root=/dev/$bdev rw " \ 897 "console=$consoledev,$baudrate $othbootargs;" \ 898 "tftp $loadaddr $bootfile;" \ 899 "tftp $fdtaddr $fdtfile;" \ 900 "bootm $loadaddr - $fdtaddr" 901 902 #define CONFIG_NFSBOOTCOMMAND \ 903 "setenv bootargs root=/dev/nfs rw " \ 904 "nfsroot=$serverip:$rootpath " \ 905 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 906 "console=$consoledev,$baudrate $othbootargs;" \ 907 "tftp $loadaddr $bootfile;" \ 908 "tftp $fdtaddr $fdtfile;" \ 909 "bootm $loadaddr - $fdtaddr" 910 911 #define CONFIG_RAMBOOTCOMMAND \ 912 "setenv bootargs root=/dev/ram rw " \ 913 "console=$consoledev,$baudrate $othbootargs;" \ 914 "tftp $ramdiskaddr $ramdiskfile;" \ 915 "tftp $loadaddr $bootfile;" \ 916 "tftp $fdtaddr $fdtfile;" \ 917 "bootm $loadaddr $ramdiskaddr $fdtaddr" 918 919 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 920 921 #include <asm/fsl_secure_boot.h> 922 923 #endif /* __CONFIG_H */ 924