1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * B4860 QDS board configuration file 28 */ 29 #define CONFIG_B4860QDS 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #endif 36 37 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 38 /* Set 1M boot space */ 39 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 41 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 42 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 43 #define CONFIG_SYS_NO_FLASH 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_BOOKE 48 #define CONFIG_E500 /* BOOKE e500 family */ 49 #define CONFIG_E500MC /* BOOKE e500mc family */ 50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 51 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 52 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 53 #define CONFIG_MP /* support multiple processors */ 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xeff80000 57 #endif 58 59 #ifndef CONFIG_RESET_VECTOR_ADDRESS 60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 61 #endif 62 63 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 64 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 65 #define CONFIG_FSL_IFC /* Enable IFC Support */ 66 #define CONFIG_PCI /* Enable PCI/PCIE */ 67 #define CONFIG_PCIE1 /* PCIE controler 1 */ 68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 70 71 #ifndef CONFIG_PPC_B4420 72 #define CONFIG_SYS_SRIO 73 #define CONFIG_SRIO1 /* SRIO port 1 */ 74 #define CONFIG_SRIO2 /* SRIO port 2 */ 75 #define CONFIG_SRIO_PCIE_BOOT_MASTER 76 #endif 77 78 #define CONFIG_FSL_LAW /* Use common FSL init code */ 79 80 /* I2C bus multiplexer */ 81 #define I2C_MUX_PCA_ADDR 0x77 82 83 /* VSC Crossbar switches */ 84 #define CONFIG_VSC_CROSSBAR 85 #define I2C_CH_DEFAULT 0x8 86 #define I2C_CH_VSC3316 0xc 87 #define I2C_CH_VSC3308 0xd 88 89 #define VSC3316_TX_ADDRESS 0x70 90 #define VSC3316_RX_ADDRESS 0x71 91 #define VSC3308_TX_ADDRESS 0x02 92 #define VSC3308_RX_ADDRESS 0x03 93 94 #define CONFIG_ENV_OVERWRITE 95 96 #ifdef CONFIG_SYS_NO_FLASH 97 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 98 #define CONFIG_ENV_IS_NOWHERE 99 #endif 100 #else 101 #define CONFIG_FLASH_CFI_DRIVER 102 #define CONFIG_SYS_FLASH_CFI 103 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 104 #endif 105 106 #if defined(CONFIG_SPIFLASH) 107 #define CONFIG_SYS_EXTRA_ENV_RELOC 108 #define CONFIG_ENV_IS_IN_SPI_FLASH 109 #define CONFIG_ENV_SPI_BUS 0 110 #define CONFIG_ENV_SPI_CS 0 111 #define CONFIG_ENV_SPI_MAX_HZ 10000000 112 #define CONFIG_ENV_SPI_MODE 0 113 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 114 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 115 #define CONFIG_ENV_SECT_SIZE 0x10000 116 #elif defined(CONFIG_SDCARD) 117 #define CONFIG_SYS_EXTRA_ENV_RELOC 118 #define CONFIG_ENV_IS_IN_MMC 119 #define CONFIG_SYS_MMC_ENV_DEV 0 120 #define CONFIG_ENV_SIZE 0x2000 121 #define CONFIG_ENV_OFFSET (512 * 1097) 122 #elif defined(CONFIG_NAND) 123 #define CONFIG_SYS_EXTRA_ENV_RELOC 124 #define CONFIG_ENV_IS_IN_NAND 125 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 126 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 127 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 128 #define CONFIG_ENV_IS_IN_REMOTE 129 #define CONFIG_ENV_ADDR 0xffe20000 130 #define CONFIG_ENV_SIZE 0x2000 131 #elif defined(CONFIG_ENV_IS_NOWHERE) 132 #define CONFIG_ENV_SIZE 0x2000 133 #else 134 #define CONFIG_ENV_IS_IN_FLASH 135 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 136 #define CONFIG_ENV_SIZE 0x2000 137 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 138 #endif 139 140 #ifndef __ASSEMBLY__ 141 unsigned long get_board_sys_clk(void); 142 unsigned long get_board_ddr_clk(void); 143 #endif 144 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 145 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 146 147 /* 148 * These can be toggled for performance analysis, otherwise use default. 149 */ 150 #define CONFIG_SYS_CACHE_STASHING 151 #define CONFIG_BTB /* toggle branch predition */ 152 #define CONFIG_DDR_ECC 153 #ifdef CONFIG_DDR_ECC 154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 155 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 156 #endif 157 158 #define CONFIG_ENABLE_36BIT_PHYS 159 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_ADDR_MAP 162 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 163 #endif 164 165 #if 0 166 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 167 #endif 168 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 169 #define CONFIG_SYS_MEMTEST_END 0x00400000 170 #define CONFIG_SYS_ALT_MEMTEST 171 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 172 173 /* 174 * Config the L3 Cache as L3 SRAM 175 */ 176 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 177 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_DCSRBAR 0xf0000000 180 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 181 #endif 182 183 /* EEPROM */ 184 #define CONFIG_SYS_I2C_EEPROM_NXID 185 #define CONFIG_SYS_EEPROM_BUS_NUM 0 186 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 187 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 190 191 /* 192 * DDR Setup 193 */ 194 #define CONFIG_VERY_BIG_RAM 195 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 196 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 197 198 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 199 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 200 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 201 202 #define CONFIG_DDR_SPD 203 #define CONFIG_SYS_DDR_RAW_TIMING 204 #define CONFIG_FSL_DDR3 205 #define CONFIG_FSL_DDR_INTERACTIVE 206 207 #define CONFIG_SYS_SPD_BUS_NUM 0 208 #define SPD_EEPROM_ADDRESS1 0x51 209 #define SPD_EEPROM_ADDRESS2 0x53 210 211 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 212 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 213 214 /* 215 * IFC Definitions 216 */ 217 #define CONFIG_SYS_FLASH_BASE 0xe0000000 218 #ifdef CONFIG_PHYS_64BIT 219 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 220 #else 221 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 222 #endif 223 224 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 225 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 226 + 0x8000000) | \ 227 CSPR_PORT_SIZE_16 | \ 228 CSPR_MSEL_NOR | \ 229 CSPR_V) 230 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 231 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 232 CSPR_PORT_SIZE_16 | \ 233 CSPR_MSEL_NOR | \ 234 CSPR_V) 235 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 236 /* NOR Flash Timing Params */ 237 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 238 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 239 FTIM0_NOR_TEADC(0x04) | \ 240 FTIM0_NOR_TEAHC(0x20)) 241 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 242 FTIM1_NOR_TRAD_NOR(0x1A) |\ 243 FTIM1_NOR_TSEQRAD_NOR(0x13)) 244 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 245 FTIM2_NOR_TCH(0x0E) | \ 246 FTIM2_NOR_TWPH(0x0E) | \ 247 FTIM2_NOR_TWP(0x1c)) 248 #define CONFIG_SYS_NOR_FTIM3 0x0 249 250 #define CONFIG_SYS_FLASH_QUIET_TEST 251 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 252 253 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 254 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 257 258 #define CONFIG_SYS_FLASH_EMPTY_INFO 259 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 260 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 261 262 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 263 #define CONFIG_FSL_QIXIS_V2 264 #define QIXIS_BASE 0xffdf0000 265 #ifdef CONFIG_PHYS_64BIT 266 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 267 #else 268 #define QIXIS_BASE_PHYS QIXIS_BASE 269 #endif 270 #define QIXIS_LBMAP_SWITCH 0x01 271 #define QIXIS_LBMAP_MASK 0x0f 272 #define QIXIS_LBMAP_SHIFT 0 273 #define QIXIS_LBMAP_DFLTBANK 0x00 274 #define QIXIS_LBMAP_ALTBANK 0x02 275 #define QIXIS_RST_CTL_RESET 0x31 276 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 277 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 278 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 279 280 #define CONFIG_SYS_CSPR3_EXT (0xf) 281 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 282 | CSPR_PORT_SIZE_8 \ 283 | CSPR_MSEL_GPCM \ 284 | CSPR_V) 285 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 286 #define CONFIG_SYS_CSOR3 0x0 287 /* QIXIS Timing parameters for IFC CS3 */ 288 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 289 FTIM0_GPCM_TEADC(0x0e) | \ 290 FTIM0_GPCM_TEAHC(0x0e)) 291 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 292 FTIM1_GPCM_TRAD(0x1f)) 293 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 294 FTIM2_GPCM_TCH(0x0) | \ 295 FTIM2_GPCM_TWP(0x1f)) 296 #define CONFIG_SYS_CS3_FTIM3 0x0 297 298 /* NAND Flash on IFC */ 299 #define CONFIG_NAND_FSL_IFC 300 #define CONFIG_SYS_NAND_BASE 0xff800000 301 #ifdef CONFIG_PHYS_64BIT 302 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 303 #else 304 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 305 #endif 306 307 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 308 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 309 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 310 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 311 | CSPR_V) 312 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 313 314 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 315 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 316 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 317 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 318 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 319 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 320 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 321 322 #define CONFIG_SYS_NAND_ONFI_DETECTION 323 324 /* ONFI NAND Flash mode0 Timing Params */ 325 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 326 FTIM0_NAND_TWP(0x18) | \ 327 FTIM0_NAND_TWCHT(0x07) | \ 328 FTIM0_NAND_TWH(0x0a)) 329 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 330 FTIM1_NAND_TWBE(0x39) | \ 331 FTIM1_NAND_TRR(0x0e) | \ 332 FTIM1_NAND_TRP(0x18)) 333 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 334 FTIM2_NAND_TREH(0x0a) | \ 335 FTIM2_NAND_TWHRE(0x1e)) 336 #define CONFIG_SYS_NAND_FTIM3 0x0 337 338 #define CONFIG_SYS_NAND_DDR_LAW 11 339 340 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 341 #define CONFIG_SYS_MAX_NAND_DEVICE 1 342 #define CONFIG_MTD_NAND_VERIFY_WRITE 343 #define CONFIG_CMD_NAND 344 345 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 346 347 #if defined(CONFIG_NAND) 348 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 349 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 350 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 351 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 352 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 353 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 354 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 355 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 356 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 357 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 358 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 359 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 360 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 361 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 362 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 363 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 364 #else 365 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 366 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 367 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 368 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 369 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 370 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 371 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 372 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 373 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 374 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 375 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 376 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 377 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 378 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 379 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 380 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 381 #endif 382 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 383 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 384 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 385 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 386 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 387 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 388 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 389 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 390 391 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 392 393 #if defined(CONFIG_RAMBOOT_PBL) 394 #define CONFIG_SYS_RAMBOOT 395 #endif 396 397 #define CONFIG_BOARD_EARLY_INIT_R 398 #define CONFIG_MISC_INIT_R 399 400 #define CONFIG_HWCONFIG 401 402 /* define to use L1 as initial stack */ 403 #define CONFIG_L1_INIT_RAM 404 #define CONFIG_SYS_INIT_RAM_LOCK 405 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 409 /* The assembler doesn't like typecast */ 410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 411 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 412 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 413 #else 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 417 #endif 418 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 419 420 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 421 GENERATED_GBL_DATA_SIZE) 422 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 423 424 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 425 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 426 427 /* Serial Port - controlled on board with jumper J8 428 * open - index 2 429 * shorted - index 1 430 */ 431 #define CONFIG_CONS_INDEX 1 432 #define CONFIG_SYS_NS16550 433 #define CONFIG_SYS_NS16550_SERIAL 434 #define CONFIG_SYS_NS16550_REG_SIZE 1 435 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 436 437 #define CONFIG_SYS_BAUDRATE_TABLE \ 438 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 439 440 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 441 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 442 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 443 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 444 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 445 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 446 447 448 /* Use the HUSH parser */ 449 #define CONFIG_SYS_HUSH_PARSER 450 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 451 452 /* pass open firmware flat tree */ 453 #define CONFIG_OF_LIBFDT 454 #define CONFIG_OF_BOARD_SETUP 455 #define CONFIG_OF_STDOUT_VIA_ALIAS 456 457 /* new uImage format support */ 458 #define CONFIG_FIT 459 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 460 461 /* I2C */ 462 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 463 #define CONFIG_HARD_I2C /* I2C with hardware support */ 464 #define CONFIG_I2C_MULTI_BUS 465 #define CONFIG_I2C_CMD_TREE 466 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */ 467 #define CONFIG_SYS_I2C_SLAVE 0x7F 468 #define CONFIG_SYS_I2C_OFFSET 0x118000 469 #define CONFIG_SYS_I2C2_OFFSET 0x119000 470 471 /* 472 * RTC configuration 473 */ 474 #define RTC 475 #define CONFIG_RTC_DS3231 1 476 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 477 478 /* 479 * RapidIO 480 */ 481 #ifdef CONFIG_SYS_SRIO 482 #ifdef CONFIG_SRIO1 483 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 484 #ifdef CONFIG_PHYS_64BIT 485 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 486 #else 487 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 488 #endif 489 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 490 #endif 491 492 #ifdef CONFIG_SRIO2 493 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 494 #ifdef CONFIG_PHYS_64BIT 495 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 496 #else 497 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 498 #endif 499 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 500 #endif 501 #endif 502 503 /* 504 * for slave u-boot IMAGE instored in master memory space, 505 * PHYS must be aligned based on the SIZE 506 */ 507 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 511 /* 512 * for slave UCODE and ENV instored in master memory space, 513 * PHYS must be aligned based on the SIZE 514 */ 515 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 516 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 518 519 /* slave core release by master*/ 520 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 521 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 522 523 /* 524 * SRIO_PCIE_BOOT - SLAVE 525 */ 526 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 527 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 528 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 529 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 530 #endif 531 532 /* 533 * eSPI - Enhanced SPI 534 */ 535 #define CONFIG_FSL_ESPI 536 #define CONFIG_SPI_FLASH 537 #define CONFIG_SPI_FLASH_SST 538 #define CONFIG_CMD_SF 539 #define CONFIG_SF_DEFAULT_SPEED 10000000 540 #define CONFIG_SF_DEFAULT_MODE 0 541 542 /* 543 * MAPLE 544 */ 545 #ifdef CONFIG_PHYS_64BIT 546 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 547 #else 548 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 549 #endif 550 551 /* 552 * General PCI 553 * Memory space is mapped 1-1, but I/O space must start from 0. 554 */ 555 556 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 557 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 558 #ifdef CONFIG_PHYS_64BIT 559 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 560 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 561 #else 562 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 563 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 564 #endif 565 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 566 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 567 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 570 #else 571 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 572 #endif 573 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 574 575 /* Qman/Bman */ 576 #ifndef CONFIG_NOBQFMAN 577 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 578 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 579 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 582 #else 583 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 584 #endif 585 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 586 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 587 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 590 #else 591 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 592 #endif 593 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 594 595 #define CONFIG_SYS_DPAA_FMAN 596 597 /* Default address of microcode for the Linux Fman driver */ 598 #if defined(CONFIG_SPIFLASH) 599 /* 600 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 601 * env, so we got 0x110000. 602 */ 603 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 604 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 605 #elif defined(CONFIG_SDCARD) 606 /* 607 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 608 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 609 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 610 */ 611 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 612 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 613 #elif defined(CONFIG_NAND) 614 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 615 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 617 /* 618 * Slave has no ucode locally, it can fetch this from remote. When implementing 619 * in two corenet boards, slave's ucode could be stored in master's memory 620 * space, the address can be mapped from slave TLB->slave LAW-> 621 * slave SRIO or PCIE outbound window->master inbound window-> 622 * master LAW->the ucode address in master's memory space. 623 */ 624 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 625 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 626 #else 627 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 628 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 629 #endif 630 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 631 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 632 #endif /* CONFIG_NOBQFMAN */ 633 634 #ifdef CONFIG_SYS_DPAA_FMAN 635 #define CONFIG_FMAN_ENET 636 #define CONFIG_PHYLIB_10G 637 #define CONFIG_PHY_VITESSE 638 #define CONFIG_PHY_TERANETICS 639 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 640 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 641 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 642 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 643 #endif 644 645 #ifdef CONFIG_PCI 646 #define CONFIG_PCI_INDIRECT_BRIDGE 647 #define CONFIG_NET_MULTI 648 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 649 #define CONFIG_E1000 650 651 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 652 #define CONFIG_DOS_PARTITION 653 #endif /* CONFIG_PCI */ 654 655 #ifdef CONFIG_FMAN_ENET 656 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 657 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 658 659 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 660 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 661 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 662 663 664 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 665 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 666 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 667 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 668 669 #define CONFIG_MII /* MII PHY management */ 670 #define CONFIG_ETHPRIME "FM1@DTSEC1" 671 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 672 #endif 673 674 /* 675 * Environment 676 */ 677 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 678 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 679 680 /* 681 * Command line configuration. 682 */ 683 #include <config_cmd_default.h> 684 685 #define CONFIG_CMD_DATE 686 #define CONFIG_CMD_DHCP 687 #define CONFIG_CMD_EEPROM 688 #define CONFIG_CMD_ELF 689 #define CONFIG_CMD_ERRATA 690 #define CONFIG_CMD_GREPENV 691 #define CONFIG_CMD_IRQ 692 #define CONFIG_CMD_I2C 693 #define CONFIG_CMD_MII 694 #define CONFIG_CMD_PING 695 #define CONFIG_CMD_REGINFO 696 #define CONFIG_CMD_SETEXPR 697 698 #ifdef CONFIG_PCI 699 #define CONFIG_CMD_PCI 700 #define CONFIG_CMD_NET 701 #endif 702 703 /* 704 * USB 705 */ 706 #define CONFIG_HAS_FSL_DR_USB 707 708 #ifdef CONFIG_HAS_FSL_DR_USB 709 #define CONFIG_USB_EHCI 710 711 #ifdef CONFIG_USB_EHCI 712 #define CONFIG_CMD_USB 713 #define CONFIG_USB_STORAGE 714 #define CONFIG_USB_EHCI_FSL 715 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 716 #define CONFIG_CMD_EXT2 717 #endif 718 #endif 719 720 /* 721 * Miscellaneous configurable options 722 */ 723 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 724 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 725 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 726 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 727 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 728 #ifdef CONFIG_CMD_KGDB 729 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 730 #else 731 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 732 #endif 733 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 734 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 735 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 736 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 737 738 /* 739 * For booting Linux, the board info and command line data 740 * have to be in the first 64 MB of memory, since this is 741 * the maximum mapped by the Linux kernel during initialization. 742 */ 743 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 744 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 745 746 #ifdef CONFIG_CMD_KGDB 747 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 748 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 749 #endif 750 751 /* 752 * Environment Configuration 753 */ 754 #define CONFIG_ROOTPATH "/opt/nfsroot" 755 #define CONFIG_BOOTFILE "uImage" 756 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 757 758 /* default location for tftp and bootm */ 759 #define CONFIG_LOADADDR 1000000 760 761 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 762 763 #define CONFIG_BAUDRATE 115200 764 765 #define __USB_PHY_TYPE ulpi 766 767 #define CONFIG_EXTRA_ENV_SETTINGS \ 768 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 769 "bank_intlv=cs0_cs1;" \ 770 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 771 "netdev=eth0\0" \ 772 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 773 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 774 "tftpflash=tftpboot $loadaddr $uboot && " \ 775 "protect off $ubootaddr +$filesize && " \ 776 "erase $ubootaddr +$filesize && " \ 777 "cp.b $loadaddr $ubootaddr $filesize && " \ 778 "protect on $ubootaddr +$filesize && " \ 779 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 780 "consoledev=ttyS0\0" \ 781 "ramdiskaddr=2000000\0" \ 782 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 783 "fdtaddr=c00000\0" \ 784 "fdtfile=b4860qds/b4860qds.dtb\0" \ 785 "bdev=sda3\0" \ 786 "c=ffe\0" 787 788 /* For emulation this causes u-boot to jump to the start of the proof point 789 app code automatically */ 790 #define CONFIG_PROOF_POINTS \ 791 "setenv bootargs root=/dev/$bdev rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "cpu 1 release 0x29000000 - - -;" \ 794 "cpu 2 release 0x29000000 - - -;" \ 795 "cpu 3 release 0x29000000 - - -;" \ 796 "cpu 4 release 0x29000000 - - -;" \ 797 "cpu 5 release 0x29000000 - - -;" \ 798 "cpu 6 release 0x29000000 - - -;" \ 799 "cpu 7 release 0x29000000 - - -;" \ 800 "go 0x29000000" 801 802 #define CONFIG_HVBOOT \ 803 "setenv bootargs config-addr=0x60000000; " \ 804 "bootm 0x01000000 - 0x00f00000" 805 806 #define CONFIG_ALU \ 807 "setenv bootargs root=/dev/$bdev rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "cpu 1 release 0x01000000 - - -;" \ 810 "cpu 2 release 0x01000000 - - -;" \ 811 "cpu 3 release 0x01000000 - - -;" \ 812 "cpu 4 release 0x01000000 - - -;" \ 813 "cpu 5 release 0x01000000 - - -;" \ 814 "cpu 6 release 0x01000000 - - -;" \ 815 "cpu 7 release 0x01000000 - - -;" \ 816 "go 0x01000000" 817 818 #define CONFIG_LINUX \ 819 "setenv bootargs root=/dev/ram rw " \ 820 "console=$consoledev,$baudrate $othbootargs;" \ 821 "setenv ramdiskaddr 0x02000000;" \ 822 "setenv fdtaddr 0x00c00000;" \ 823 "setenv loadaddr 0x1000000;" \ 824 "bootm $loadaddr $ramdiskaddr $fdtaddr" 825 826 #define CONFIG_HDBOOT \ 827 "setenv bootargs root=/dev/$bdev rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "tftp $loadaddr $bootfile;" \ 830 "tftp $fdtaddr $fdtfile;" \ 831 "bootm $loadaddr - $fdtaddr" 832 833 #define CONFIG_NFSBOOTCOMMAND \ 834 "setenv bootargs root=/dev/nfs rw " \ 835 "nfsroot=$serverip:$rootpath " \ 836 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 837 "console=$consoledev,$baudrate $othbootargs;" \ 838 "tftp $loadaddr $bootfile;" \ 839 "tftp $fdtaddr $fdtfile;" \ 840 "bootm $loadaddr - $fdtaddr" 841 842 #define CONFIG_RAMBOOTCOMMAND \ 843 "setenv bootargs root=/dev/ram rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "tftp $ramdiskaddr $ramdiskfile;" \ 846 "tftp $loadaddr $bootfile;" \ 847 "tftp $fdtaddr $fdtfile;" \ 848 "bootm $loadaddr $ramdiskaddr $fdtaddr" 849 850 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 851 852 #ifdef CONFIG_SECURE_BOOT 853 #include <asm/fsl_secure_boot.h> 854 #endif 855 856 #endif /* __CONFIG_H */ 857