1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_FSL_LAW /* Use common FSL init code */ 23 #define CONFIG_SYS_TEXT_BASE 0x00201000 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #define RESET_VECTOR_OFFSET 0x27FFC 28 #define BOOT_PAGE_OFFSET 0x27000 29 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 30 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 31 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 32 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 33 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 34 #define CONFIG_SPL_NAND_BOOT 35 #ifdef CONFIG_SPL_BUILD 36 #define CONFIG_SPL_SKIP_RELOCATE 37 #define CONFIG_SPL_COMMON_INIT_DDR 38 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 39 #define CONFIG_SYS_NO_FLASH 40 #endif 41 #endif 42 #endif 43 44 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 45 /* Set 1M boot space */ 46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 47 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 48 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 49 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 50 #define CONFIG_SYS_NO_FLASH 51 #endif 52 53 /* High Level Configuration Options */ 54 #define CONFIG_BOOKE 55 #define CONFIG_E500 /* BOOKE e500 family */ 56 #define CONFIG_E500MC /* BOOKE e500mc family */ 57 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 58 #define CONFIG_MP /* support multiple processors */ 59 60 #ifndef CONFIG_SYS_TEXT_BASE 61 #define CONFIG_SYS_TEXT_BASE 0xeff40000 62 #endif 63 64 #ifndef CONFIG_RESET_VECTOR_ADDRESS 65 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 66 #endif 67 68 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 69 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 70 #define CONFIG_FSL_IFC /* Enable IFC Support */ 71 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 72 #define CONFIG_PCIE1 /* PCIE controller 1 */ 73 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 74 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 75 76 #ifndef CONFIG_ARCH_B4420 77 #define CONFIG_SYS_SRIO 78 #define CONFIG_SRIO1 /* SRIO port 1 */ 79 #define CONFIG_SRIO2 /* SRIO port 2 */ 80 #define CONFIG_SRIO_PCIE_BOOT_MASTER 81 #endif 82 83 #define CONFIG_FSL_LAW /* Use common FSL init code */ 84 85 /* I2C bus multiplexer */ 86 #define I2C_MUX_PCA_ADDR 0x77 87 88 /* VSC Crossbar switches */ 89 #define CONFIG_VSC_CROSSBAR 90 #define I2C_CH_DEFAULT 0x8 91 #define I2C_CH_VSC3316 0xc 92 #define I2C_CH_VSC3308 0xd 93 94 #define VSC3316_TX_ADDRESS 0x70 95 #define VSC3316_RX_ADDRESS 0x71 96 #define VSC3308_TX_ADDRESS 0x02 97 #define VSC3308_RX_ADDRESS 0x03 98 99 /* IDT clock synthesizers */ 100 #define CONFIG_IDT8T49N222A 101 #define I2C_CH_IDT 0x9 102 103 #define IDT_SERDES1_ADDRESS 0x6E 104 #define IDT_SERDES2_ADDRESS 0x6C 105 106 /* Voltage monitor on channel 2*/ 107 #define I2C_MUX_CH_VOL_MONITOR 0xa 108 #define I2C_VOL_MONITOR_ADDR 0x40 109 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 110 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 111 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 112 113 #define CONFIG_ZM7300 114 #define I2C_MUX_CH_DPM 0xa 115 #define I2C_DPM_ADDR 0x28 116 117 #define CONFIG_ENV_OVERWRITE 118 119 #ifdef CONFIG_SYS_NO_FLASH 120 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 121 #define CONFIG_ENV_IS_NOWHERE 122 #endif 123 #else 124 #define CONFIG_FLASH_CFI_DRIVER 125 #define CONFIG_SYS_FLASH_CFI 126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 127 #endif 128 129 #if defined(CONFIG_SPIFLASH) 130 #define CONFIG_SYS_EXTRA_ENV_RELOC 131 #define CONFIG_ENV_IS_IN_SPI_FLASH 132 #define CONFIG_ENV_SPI_BUS 0 133 #define CONFIG_ENV_SPI_CS 0 134 #define CONFIG_ENV_SPI_MAX_HZ 10000000 135 #define CONFIG_ENV_SPI_MODE 0 136 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 137 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 138 #define CONFIG_ENV_SECT_SIZE 0x10000 139 #elif defined(CONFIG_SDCARD) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_IS_IN_MMC 142 #define CONFIG_SYS_MMC_ENV_DEV 0 143 #define CONFIG_ENV_SIZE 0x2000 144 #define CONFIG_ENV_OFFSET (512 * 1097) 145 #elif defined(CONFIG_NAND) 146 #define CONFIG_SYS_EXTRA_ENV_RELOC 147 #define CONFIG_ENV_IS_IN_NAND 148 #define CONFIG_ENV_SIZE 0x2000 149 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 150 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 151 #define CONFIG_ENV_IS_IN_REMOTE 152 #define CONFIG_ENV_ADDR 0xffe20000 153 #define CONFIG_ENV_SIZE 0x2000 154 #elif defined(CONFIG_ENV_IS_NOWHERE) 155 #define CONFIG_ENV_SIZE 0x2000 156 #else 157 #define CONFIG_ENV_IS_IN_FLASH 158 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 161 #endif 162 163 #ifndef __ASSEMBLY__ 164 unsigned long get_board_sys_clk(void); 165 unsigned long get_board_ddr_clk(void); 166 #endif 167 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 168 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 169 170 /* 171 * These can be toggled for performance analysis, otherwise use default. 172 */ 173 #define CONFIG_SYS_CACHE_STASHING 174 #define CONFIG_BTB /* toggle branch predition */ 175 #define CONFIG_DDR_ECC 176 #ifdef CONFIG_DDR_ECC 177 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 178 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 179 #endif 180 181 #define CONFIG_ENABLE_36BIT_PHYS 182 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_ADDR_MAP 185 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 186 #endif 187 188 #if 0 189 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 190 #endif 191 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 192 #define CONFIG_SYS_MEMTEST_END 0x00400000 193 #define CONFIG_SYS_ALT_MEMTEST 194 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 195 196 /* 197 * Config the L3 Cache as L3 SRAM 198 */ 199 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 200 #define CONFIG_SYS_L3_SIZE 256 << 10 201 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 202 #ifdef CONFIG_NAND 203 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 204 #endif 205 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 206 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 207 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 208 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 209 210 #ifdef CONFIG_PHYS_64BIT 211 #define CONFIG_SYS_DCSRBAR 0xf0000000 212 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 213 #endif 214 215 /* EEPROM */ 216 #define CONFIG_ID_EEPROM 217 #define CONFIG_SYS_I2C_EEPROM_NXID 218 #define CONFIG_SYS_EEPROM_BUS_NUM 0 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 223 224 /* 225 * DDR Setup 226 */ 227 #define CONFIG_VERY_BIG_RAM 228 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 229 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 230 231 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 232 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 233 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 234 235 #define CONFIG_DDR_SPD 236 #define CONFIG_SYS_DDR_RAW_TIMING 237 #define CONFIG_SYS_FSL_DDR3 238 #ifndef CONFIG_SPL_BUILD 239 #define CONFIG_FSL_DDR_INTERACTIVE 240 #endif 241 242 #define CONFIG_SYS_SPD_BUS_NUM 0 243 #define SPD_EEPROM_ADDRESS1 0x51 244 #define SPD_EEPROM_ADDRESS2 0x53 245 246 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 247 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 248 249 /* 250 * IFC Definitions 251 */ 252 #define CONFIG_SYS_FLASH_BASE 0xe0000000 253 #ifdef CONFIG_PHYS_64BIT 254 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 255 #else 256 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 257 #endif 258 259 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 261 + 0x8000000) | \ 262 CSPR_PORT_SIZE_16 | \ 263 CSPR_MSEL_NOR | \ 264 CSPR_V) 265 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 266 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 267 CSPR_PORT_SIZE_16 | \ 268 CSPR_MSEL_NOR | \ 269 CSPR_V) 270 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 271 /* NOR Flash Timing Params */ 272 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 273 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 274 FTIM0_NOR_TEADC(0x04) | \ 275 FTIM0_NOR_TEAHC(0x20)) 276 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 277 FTIM1_NOR_TRAD_NOR(0x1A) |\ 278 FTIM1_NOR_TSEQRAD_NOR(0x13)) 279 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 280 FTIM2_NOR_TCH(0x0E) | \ 281 FTIM2_NOR_TWPH(0x0E) | \ 282 FTIM2_NOR_TWP(0x1c)) 283 #define CONFIG_SYS_NOR_FTIM3 0x0 284 285 #define CONFIG_SYS_FLASH_QUIET_TEST 286 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 287 288 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 289 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 290 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 291 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 292 293 #define CONFIG_SYS_FLASH_EMPTY_INFO 294 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 295 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 296 297 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 298 #define CONFIG_FSL_QIXIS_V2 299 #define QIXIS_BASE 0xffdf0000 300 #ifdef CONFIG_PHYS_64BIT 301 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 302 #else 303 #define QIXIS_BASE_PHYS QIXIS_BASE 304 #endif 305 #define QIXIS_LBMAP_SWITCH 0x01 306 #define QIXIS_LBMAP_MASK 0x0f 307 #define QIXIS_LBMAP_SHIFT 0 308 #define QIXIS_LBMAP_DFLTBANK 0x00 309 #define QIXIS_LBMAP_ALTBANK 0x02 310 #define QIXIS_RST_CTL_RESET 0x31 311 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 312 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 313 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 314 315 #define CONFIG_SYS_CSPR3_EXT (0xf) 316 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 317 | CSPR_PORT_SIZE_8 \ 318 | CSPR_MSEL_GPCM \ 319 | CSPR_V) 320 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 321 #define CONFIG_SYS_CSOR3 0x0 322 /* QIXIS Timing parameters for IFC CS3 */ 323 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 324 FTIM0_GPCM_TEADC(0x0e) | \ 325 FTIM0_GPCM_TEAHC(0x0e)) 326 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 327 FTIM1_GPCM_TRAD(0x1f)) 328 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 329 FTIM2_GPCM_TCH(0x8) | \ 330 FTIM2_GPCM_TWP(0x1f)) 331 #define CONFIG_SYS_CS3_FTIM3 0x0 332 333 /* NAND Flash on IFC */ 334 #define CONFIG_NAND_FSL_IFC 335 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 336 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 337 #define CONFIG_SYS_NAND_BASE 0xff800000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 340 #else 341 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 342 #endif 343 344 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 345 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 346 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 347 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 348 | CSPR_V) 349 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 350 351 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 352 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 353 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 354 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 355 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 356 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 357 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 358 359 #define CONFIG_SYS_NAND_ONFI_DETECTION 360 361 /* ONFI NAND Flash mode0 Timing Params */ 362 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 363 FTIM0_NAND_TWP(0x18) | \ 364 FTIM0_NAND_TWCHT(0x07) | \ 365 FTIM0_NAND_TWH(0x0a)) 366 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 367 FTIM1_NAND_TWBE(0x39) | \ 368 FTIM1_NAND_TRR(0x0e) | \ 369 FTIM1_NAND_TRP(0x18)) 370 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 371 FTIM2_NAND_TREH(0x0a) | \ 372 FTIM2_NAND_TWHRE(0x1e)) 373 #define CONFIG_SYS_NAND_FTIM3 0x0 374 375 #define CONFIG_SYS_NAND_DDR_LAW 11 376 377 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 378 #define CONFIG_SYS_MAX_NAND_DEVICE 1 379 #define CONFIG_CMD_NAND 380 381 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 382 383 #if defined(CONFIG_NAND) 384 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 385 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 386 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 387 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 388 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 389 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 390 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 391 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 392 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 393 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 394 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 395 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 396 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 397 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 398 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 399 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 400 #else 401 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 402 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 403 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 404 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 405 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 406 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 407 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 408 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 409 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 410 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 411 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 412 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 413 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 414 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 415 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 416 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 417 #endif 418 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 419 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 420 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 421 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 422 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 423 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 424 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 425 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 426 427 #ifdef CONFIG_SPL_BUILD 428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 429 #else 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 431 #endif 432 433 #if defined(CONFIG_RAMBOOT_PBL) 434 #define CONFIG_SYS_RAMBOOT 435 #endif 436 437 #define CONFIG_BOARD_EARLY_INIT_R 438 #define CONFIG_MISC_INIT_R 439 440 #define CONFIG_HWCONFIG 441 442 /* define to use L1 as initial stack */ 443 #define CONFIG_L1_INIT_RAM 444 #define CONFIG_SYS_INIT_RAM_LOCK 445 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 449 /* The assembler doesn't like typecast */ 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 451 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 452 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 453 #else 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 457 #endif 458 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 459 460 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 461 GENERATED_GBL_DATA_SIZE) 462 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 463 464 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 465 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 466 467 /* Serial Port - controlled on board with jumper J8 468 * open - index 2 469 * shorted - index 1 470 */ 471 #define CONFIG_CONS_INDEX 1 472 #define CONFIG_SYS_NS16550_SERIAL 473 #define CONFIG_SYS_NS16550_REG_SIZE 1 474 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 475 476 #define CONFIG_SYS_BAUDRATE_TABLE \ 477 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 478 479 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 480 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 481 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 482 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 483 484 /* I2C */ 485 #define CONFIG_SYS_I2C 486 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 487 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 488 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 489 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 490 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 491 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 492 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 493 494 /* 495 * RTC configuration 496 */ 497 #define RTC 498 #define CONFIG_RTC_DS3231 1 499 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 500 501 /* 502 * RapidIO 503 */ 504 #ifdef CONFIG_SYS_SRIO 505 #ifdef CONFIG_SRIO1 506 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 507 #ifdef CONFIG_PHYS_64BIT 508 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 509 #else 510 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 511 #endif 512 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 513 #endif 514 515 #ifdef CONFIG_SRIO2 516 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 517 #ifdef CONFIG_PHYS_64BIT 518 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 519 #else 520 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 521 #endif 522 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 523 #endif 524 #endif 525 526 /* 527 * for slave u-boot IMAGE instored in master memory space, 528 * PHYS must be aligned based on the SIZE 529 */ 530 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 531 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 532 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 533 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 534 /* 535 * for slave UCODE and ENV instored in master memory space, 536 * PHYS must be aligned based on the SIZE 537 */ 538 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 539 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 540 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 541 542 /* slave core release by master*/ 543 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 544 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 545 546 /* 547 * SRIO_PCIE_BOOT - SLAVE 548 */ 549 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 550 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 551 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 552 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 553 #endif 554 555 /* 556 * eSPI - Enhanced SPI 557 */ 558 #define CONFIG_SF_DEFAULT_SPEED 10000000 559 #define CONFIG_SF_DEFAULT_MODE 0 560 561 /* 562 * MAPLE 563 */ 564 #ifdef CONFIG_PHYS_64BIT 565 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 566 #else 567 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 568 #endif 569 570 /* 571 * General PCI 572 * Memory space is mapped 1-1, but I/O space must start from 0. 573 */ 574 575 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 576 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 577 #ifdef CONFIG_PHYS_64BIT 578 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 580 #else 581 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 582 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 583 #endif 584 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 585 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 586 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 587 #ifdef CONFIG_PHYS_64BIT 588 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 589 #else 590 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 591 #endif 592 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 593 594 /* Qman/Bman */ 595 #ifndef CONFIG_NOBQFMAN 596 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 597 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 598 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 601 #else 602 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 603 #endif 604 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 605 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 606 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 607 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 608 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 609 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 610 CONFIG_SYS_BMAN_CENA_SIZE) 611 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 612 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 613 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 614 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 617 #else 618 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 619 #endif 620 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 621 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 622 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 623 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 624 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 626 CONFIG_SYS_QMAN_CENA_SIZE) 627 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 628 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 629 630 #define CONFIG_SYS_DPAA_FMAN 631 632 #define CONFIG_SYS_DPAA_RMAN 633 634 /* Default address of microcode for the Linux Fman driver */ 635 #if defined(CONFIG_SPIFLASH) 636 /* 637 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 638 * env, so we got 0x110000. 639 */ 640 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 641 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 642 #elif defined(CONFIG_SDCARD) 643 /* 644 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 645 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 646 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 647 */ 648 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 649 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 650 #elif defined(CONFIG_NAND) 651 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 652 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 653 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 654 /* 655 * Slave has no ucode locally, it can fetch this from remote. When implementing 656 * in two corenet boards, slave's ucode could be stored in master's memory 657 * space, the address can be mapped from slave TLB->slave LAW-> 658 * slave SRIO or PCIE outbound window->master inbound window-> 659 * master LAW->the ucode address in master's memory space. 660 */ 661 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 662 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 663 #else 664 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 665 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 666 #endif 667 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 668 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 669 #endif /* CONFIG_NOBQFMAN */ 670 671 #ifdef CONFIG_SYS_DPAA_FMAN 672 #define CONFIG_FMAN_ENET 673 #define CONFIG_PHYLIB_10G 674 #define CONFIG_PHY_VITESSE 675 #define CONFIG_PHY_TERANETICS 676 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 677 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 678 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 679 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 680 #endif 681 682 #ifdef CONFIG_PCI 683 #define CONFIG_PCI_INDIRECT_BRIDGE 684 685 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 686 #define CONFIG_DOS_PARTITION 687 #endif /* CONFIG_PCI */ 688 689 #ifdef CONFIG_FMAN_ENET 690 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 691 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 692 693 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 694 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 695 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 696 697 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 698 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 699 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 700 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 701 702 #define CONFIG_MII /* MII PHY management */ 703 #define CONFIG_ETHPRIME "FM1@DTSEC1" 704 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 705 #endif 706 707 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 708 709 /* 710 * Environment 711 */ 712 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 713 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 714 715 /* 716 * Command line configuration. 717 */ 718 #define CONFIG_CMD_DATE 719 #define CONFIG_CMD_EEPROM 720 #define CONFIG_CMD_ERRATA 721 #define CONFIG_CMD_IRQ 722 #define CONFIG_CMD_REGINFO 723 724 #ifdef CONFIG_PCI 725 #define CONFIG_CMD_PCI 726 #endif 727 728 /* Hash command with SHA acceleration supported in hardware */ 729 #ifdef CONFIG_FSL_CAAM 730 #define CONFIG_CMD_HASH 731 #define CONFIG_SHA_HW_ACCEL 732 #endif 733 734 /* 735 * USB 736 */ 737 #define CONFIG_HAS_FSL_DR_USB 738 739 #ifdef CONFIG_HAS_FSL_DR_USB 740 #define CONFIG_USB_EHCI 741 742 #ifdef CONFIG_USB_EHCI 743 #define CONFIG_USB_EHCI_FSL 744 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 745 #endif 746 #endif 747 748 /* 749 * Miscellaneous configurable options 750 */ 751 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 752 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 753 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 754 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 755 #ifdef CONFIG_CMD_KGDB 756 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 757 #else 758 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 759 #endif 760 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 761 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 762 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 763 764 /* 765 * For booting Linux, the board info and command line data 766 * have to be in the first 64 MB of memory, since this is 767 * the maximum mapped by the Linux kernel during initialization. 768 */ 769 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 770 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 771 772 #ifdef CONFIG_CMD_KGDB 773 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 774 #endif 775 776 /* 777 * Environment Configuration 778 */ 779 #define CONFIG_ROOTPATH "/opt/nfsroot" 780 #define CONFIG_BOOTFILE "uImage" 781 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 782 783 /* default location for tftp and bootm */ 784 #define CONFIG_LOADADDR 1000000 785 786 787 #define CONFIG_BAUDRATE 115200 788 789 #define __USB_PHY_TYPE ulpi 790 791 #ifdef CONFIG_ARCH_B4860 792 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 793 "bank_intlv=cs0_cs1;" \ 794 "en_cpc:cpc2;" 795 #else 796 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 797 #endif 798 799 #define CONFIG_EXTRA_ENV_SETTINGS \ 800 HWCONFIG \ 801 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 802 "netdev=eth0\0" \ 803 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 804 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 805 "tftpflash=tftpboot $loadaddr $uboot && " \ 806 "protect off $ubootaddr +$filesize && " \ 807 "erase $ubootaddr +$filesize && " \ 808 "cp.b $loadaddr $ubootaddr $filesize && " \ 809 "protect on $ubootaddr +$filesize && " \ 810 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 811 "consoledev=ttyS0\0" \ 812 "ramdiskaddr=2000000\0" \ 813 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 814 "fdtaddr=1e00000\0" \ 815 "fdtfile=b4860qds/b4860qds.dtb\0" \ 816 "bdev=sda3\0" 817 818 /* For emulation this causes u-boot to jump to the start of the proof point 819 app code automatically */ 820 #define CONFIG_PROOF_POINTS \ 821 "setenv bootargs root=/dev/$bdev rw " \ 822 "console=$consoledev,$baudrate $othbootargs;" \ 823 "cpu 1 release 0x29000000 - - -;" \ 824 "cpu 2 release 0x29000000 - - -;" \ 825 "cpu 3 release 0x29000000 - - -;" \ 826 "cpu 4 release 0x29000000 - - -;" \ 827 "cpu 5 release 0x29000000 - - -;" \ 828 "cpu 6 release 0x29000000 - - -;" \ 829 "cpu 7 release 0x29000000 - - -;" \ 830 "go 0x29000000" 831 832 #define CONFIG_HVBOOT \ 833 "setenv bootargs config-addr=0x60000000; " \ 834 "bootm 0x01000000 - 0x00f00000" 835 836 #define CONFIG_ALU \ 837 "setenv bootargs root=/dev/$bdev rw " \ 838 "console=$consoledev,$baudrate $othbootargs;" \ 839 "cpu 1 release 0x01000000 - - -;" \ 840 "cpu 2 release 0x01000000 - - -;" \ 841 "cpu 3 release 0x01000000 - - -;" \ 842 "cpu 4 release 0x01000000 - - -;" \ 843 "cpu 5 release 0x01000000 - - -;" \ 844 "cpu 6 release 0x01000000 - - -;" \ 845 "cpu 7 release 0x01000000 - - -;" \ 846 "go 0x01000000" 847 848 #define CONFIG_LINUX \ 849 "setenv bootargs root=/dev/ram rw " \ 850 "console=$consoledev,$baudrate $othbootargs;" \ 851 "setenv ramdiskaddr 0x02000000;" \ 852 "setenv fdtaddr 0x01e00000;" \ 853 "setenv loadaddr 0x1000000;" \ 854 "bootm $loadaddr $ramdiskaddr $fdtaddr" 855 856 #define CONFIG_HDBOOT \ 857 "setenv bootargs root=/dev/$bdev rw " \ 858 "console=$consoledev,$baudrate $othbootargs;" \ 859 "tftp $loadaddr $bootfile;" \ 860 "tftp $fdtaddr $fdtfile;" \ 861 "bootm $loadaddr - $fdtaddr" 862 863 #define CONFIG_NFSBOOTCOMMAND \ 864 "setenv bootargs root=/dev/nfs rw " \ 865 "nfsroot=$serverip:$rootpath " \ 866 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 867 "console=$consoledev,$baudrate $othbootargs;" \ 868 "tftp $loadaddr $bootfile;" \ 869 "tftp $fdtaddr $fdtfile;" \ 870 "bootm $loadaddr - $fdtaddr" 871 872 #define CONFIG_RAMBOOTCOMMAND \ 873 "setenv bootargs root=/dev/ram rw " \ 874 "console=$consoledev,$baudrate $othbootargs;" \ 875 "tftp $ramdiskaddr $ramdiskfile;" \ 876 "tftp $loadaddr $bootfile;" \ 877 "tftp $fdtaddr $fdtfile;" \ 878 "bootm $loadaddr $ramdiskaddr $fdtaddr" 879 880 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 881 882 #include <asm/fsl_secure_boot.h> 883 884 #endif /* __CONFIG_H */ 885