1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 23 #define CONFIG_SPL_PAD_TO 0x40000 24 #define CONFIG_SPL_MAX_SIZE 0x28000 25 #define RESET_VECTOR_OFFSET 0x27FFC 26 #define BOOT_PAGE_OFFSET 0x27000 27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 28 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 29 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 30 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 31 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 32 #define CONFIG_SPL_NAND_BOOT 33 #ifdef CONFIG_SPL_BUILD 34 #define CONFIG_SPL_SKIP_RELOCATE 35 #define CONFIG_SPL_COMMON_INIT_DDR 36 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 37 #endif 38 #endif 39 #endif 40 41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 42 /* Set 1M boot space */ 43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 47 #endif 48 49 /* High Level Configuration Options */ 50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 51 #define CONFIG_MP /* support multiple processors */ 52 53 #ifndef CONFIG_RESET_VECTOR_ADDRESS 54 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 55 #endif 56 57 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 58 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 59 #define CONFIG_PCIE1 /* PCIE controller 1 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #ifndef CONFIG_ARCH_B4420 64 #define CONFIG_SYS_SRIO 65 #define CONFIG_SRIO1 /* SRIO port 1 */ 66 #define CONFIG_SRIO2 /* SRIO port 2 */ 67 #define CONFIG_SRIO_PCIE_BOOT_MASTER 68 #endif 69 70 /* I2C bus multiplexer */ 71 #define I2C_MUX_PCA_ADDR 0x77 72 73 /* VSC Crossbar switches */ 74 #define CONFIG_VSC_CROSSBAR 75 #define I2C_CH_DEFAULT 0x8 76 #define I2C_CH_VSC3316 0xc 77 #define I2C_CH_VSC3308 0xd 78 79 #define VSC3316_TX_ADDRESS 0x70 80 #define VSC3316_RX_ADDRESS 0x71 81 #define VSC3308_TX_ADDRESS 0x02 82 #define VSC3308_RX_ADDRESS 0x03 83 84 /* IDT clock synthesizers */ 85 #define CONFIG_IDT8T49N222A 86 #define I2C_CH_IDT 0x9 87 88 #define IDT_SERDES1_ADDRESS 0x6E 89 #define IDT_SERDES2_ADDRESS 0x6C 90 91 /* Voltage monitor on channel 2*/ 92 #define I2C_MUX_CH_VOL_MONITOR 0xa 93 #define I2C_VOL_MONITOR_ADDR 0x40 94 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 95 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 96 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 97 98 #define CONFIG_ZM7300 99 #define I2C_MUX_CH_DPM 0xa 100 #define I2C_DPM_ADDR 0x28 101 102 #define CONFIG_ENV_OVERWRITE 103 104 #ifndef CONFIG_MTD_NOR_FLASH 105 #else 106 #define CONFIG_FLASH_CFI_DRIVER 107 #define CONFIG_SYS_FLASH_CFI 108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109 #endif 110 111 #if defined(CONFIG_SPIFLASH) 112 #define CONFIG_SYS_EXTRA_ENV_RELOC 113 #define CONFIG_ENV_SPI_BUS 0 114 #define CONFIG_ENV_SPI_CS 0 115 #define CONFIG_ENV_SPI_MAX_HZ 10000000 116 #define CONFIG_ENV_SPI_MODE 0 117 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 118 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 119 #define CONFIG_ENV_SECT_SIZE 0x10000 120 #elif defined(CONFIG_SDCARD) 121 #define CONFIG_SYS_EXTRA_ENV_RELOC 122 #define CONFIG_SYS_MMC_ENV_DEV 0 123 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_OFFSET (512 * 1097) 125 #elif defined(CONFIG_NAND) 126 #define CONFIG_SYS_EXTRA_ENV_RELOC 127 #define CONFIG_ENV_SIZE 0x2000 128 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 129 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 130 #define CONFIG_ENV_ADDR 0xffe20000 131 #define CONFIG_ENV_SIZE 0x2000 132 #elif defined(CONFIG_ENV_IS_NOWHERE) 133 #define CONFIG_ENV_SIZE 0x2000 134 #else 135 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 136 #define CONFIG_ENV_SIZE 0x2000 137 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 138 #endif 139 140 #ifndef __ASSEMBLY__ 141 unsigned long get_board_sys_clk(void); 142 unsigned long get_board_ddr_clk(void); 143 #endif 144 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 145 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 146 147 /* 148 * These can be toggled for performance analysis, otherwise use default. 149 */ 150 #define CONFIG_SYS_CACHE_STASHING 151 #define CONFIG_BTB /* toggle branch predition */ 152 #define CONFIG_DDR_ECC 153 #ifdef CONFIG_DDR_ECC 154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 155 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 156 #endif 157 158 #define CONFIG_ENABLE_36BIT_PHYS 159 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_ADDR_MAP 162 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 163 #endif 164 165 #if 0 166 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 167 #endif 168 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 169 #define CONFIG_SYS_MEMTEST_END 0x00400000 170 #define CONFIG_SYS_ALT_MEMTEST 171 172 /* 173 * Config the L3 Cache as L3 SRAM 174 */ 175 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 176 #define CONFIG_SYS_L3_SIZE 256 << 10 177 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 178 #ifdef CONFIG_NAND 179 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 180 #endif 181 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 182 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 183 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 184 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 185 186 #ifdef CONFIG_PHYS_64BIT 187 #define CONFIG_SYS_DCSRBAR 0xf0000000 188 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 189 #endif 190 191 /* EEPROM */ 192 #define CONFIG_ID_EEPROM 193 #define CONFIG_SYS_I2C_EEPROM_NXID 194 #define CONFIG_SYS_EEPROM_BUS_NUM 0 195 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 199 200 /* 201 * DDR Setup 202 */ 203 #define CONFIG_VERY_BIG_RAM 204 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 205 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 206 207 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 208 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 209 210 #define CONFIG_DDR_SPD 211 #define CONFIG_SYS_DDR_RAW_TIMING 212 #ifndef CONFIG_SPL_BUILD 213 #define CONFIG_FSL_DDR_INTERACTIVE 214 #endif 215 216 #define CONFIG_SYS_SPD_BUS_NUM 0 217 #define SPD_EEPROM_ADDRESS1 0x51 218 #define SPD_EEPROM_ADDRESS2 0x53 219 220 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 221 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 222 223 /* 224 * IFC Definitions 225 */ 226 #define CONFIG_SYS_FLASH_BASE 0xe0000000 227 #ifdef CONFIG_PHYS_64BIT 228 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 229 #else 230 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 231 #endif 232 233 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 234 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 235 + 0x8000000) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 240 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 241 CSPR_PORT_SIZE_16 | \ 242 CSPR_MSEL_NOR | \ 243 CSPR_V) 244 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 245 /* NOR Flash Timing Params */ 246 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 247 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 248 FTIM0_NOR_TEADC(0x04) | \ 249 FTIM0_NOR_TEAHC(0x20)) 250 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 251 FTIM1_NOR_TRAD_NOR(0x1A) |\ 252 FTIM1_NOR_TSEQRAD_NOR(0x13)) 253 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 254 FTIM2_NOR_TCH(0x0E) | \ 255 FTIM2_NOR_TWPH(0x0E) | \ 256 FTIM2_NOR_TWP(0x1c)) 257 #define CONFIG_SYS_NOR_FTIM3 0x0 258 259 #define CONFIG_SYS_FLASH_QUIET_TEST 260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 261 262 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 263 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 266 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 269 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 270 271 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 272 #define CONFIG_FSL_QIXIS_V2 273 #define QIXIS_BASE 0xffdf0000 274 #ifdef CONFIG_PHYS_64BIT 275 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 276 #else 277 #define QIXIS_BASE_PHYS QIXIS_BASE 278 #endif 279 #define QIXIS_LBMAP_SWITCH 0x01 280 #define QIXIS_LBMAP_MASK 0x0f 281 #define QIXIS_LBMAP_SHIFT 0 282 #define QIXIS_LBMAP_DFLTBANK 0x00 283 #define QIXIS_LBMAP_ALTBANK 0x02 284 #define QIXIS_RST_CTL_RESET 0x31 285 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 286 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 287 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 288 289 #define CONFIG_SYS_CSPR3_EXT (0xf) 290 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 291 | CSPR_PORT_SIZE_8 \ 292 | CSPR_MSEL_GPCM \ 293 | CSPR_V) 294 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 295 #define CONFIG_SYS_CSOR3 0x0 296 /* QIXIS Timing parameters for IFC CS3 */ 297 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 298 FTIM0_GPCM_TEADC(0x0e) | \ 299 FTIM0_GPCM_TEAHC(0x0e)) 300 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 301 FTIM1_GPCM_TRAD(0x1f)) 302 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 303 FTIM2_GPCM_TCH(0x8) | \ 304 FTIM2_GPCM_TWP(0x1f)) 305 #define CONFIG_SYS_CS3_FTIM3 0x0 306 307 /* NAND Flash on IFC */ 308 #define CONFIG_NAND_FSL_IFC 309 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 310 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 311 #define CONFIG_SYS_NAND_BASE 0xff800000 312 #ifdef CONFIG_PHYS_64BIT 313 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 314 #else 315 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 316 #endif 317 318 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 319 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 320 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 321 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 322 | CSPR_V) 323 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 324 325 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 326 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 327 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 328 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 329 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 330 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 331 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 332 333 #define CONFIG_SYS_NAND_ONFI_DETECTION 334 335 /* ONFI NAND Flash mode0 Timing Params */ 336 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 337 FTIM0_NAND_TWP(0x18) | \ 338 FTIM0_NAND_TWCHT(0x07) | \ 339 FTIM0_NAND_TWH(0x0a)) 340 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 341 FTIM1_NAND_TWBE(0x39) | \ 342 FTIM1_NAND_TRR(0x0e) | \ 343 FTIM1_NAND_TRP(0x18)) 344 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 345 FTIM2_NAND_TREH(0x0a) | \ 346 FTIM2_NAND_TWHRE(0x1e)) 347 #define CONFIG_SYS_NAND_FTIM3 0x0 348 349 #define CONFIG_SYS_NAND_DDR_LAW 11 350 351 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 352 #define CONFIG_SYS_MAX_NAND_DEVICE 1 353 354 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 355 356 #if defined(CONFIG_NAND) 357 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 365 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 366 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 367 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 368 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 369 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 370 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 371 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 372 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 373 #else 374 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 375 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 376 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 377 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 378 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 379 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 380 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 381 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 382 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 383 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 384 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 385 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 386 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 387 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 388 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 389 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 390 #endif 391 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 392 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 393 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 394 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 395 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 396 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 397 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 398 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 399 400 #ifdef CONFIG_SPL_BUILD 401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 402 #else 403 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 404 #endif 405 406 #if defined(CONFIG_RAMBOOT_PBL) 407 #define CONFIG_SYS_RAMBOOT 408 #endif 409 410 #define CONFIG_BOARD_EARLY_INIT_R 411 #define CONFIG_MISC_INIT_R 412 413 #define CONFIG_HWCONFIG 414 415 /* define to use L1 as initial stack */ 416 #define CONFIG_L1_INIT_RAM 417 #define CONFIG_SYS_INIT_RAM_LOCK 418 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 419 #ifdef CONFIG_PHYS_64BIT 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 422 /* The assembler doesn't like typecast */ 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 424 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 425 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 426 #else 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 430 #endif 431 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 432 433 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 434 GENERATED_GBL_DATA_SIZE) 435 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 436 437 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 438 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 439 440 /* Serial Port - controlled on board with jumper J8 441 * open - index 2 442 * shorted - index 1 443 */ 444 #define CONFIG_CONS_INDEX 1 445 #define CONFIG_SYS_NS16550_SERIAL 446 #define CONFIG_SYS_NS16550_REG_SIZE 1 447 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 448 449 #define CONFIG_SYS_BAUDRATE_TABLE \ 450 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 451 452 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 453 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 454 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 455 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 456 457 /* I2C */ 458 #define CONFIG_SYS_I2C 459 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 460 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 461 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 462 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 463 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 464 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 465 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 466 467 /* 468 * RTC configuration 469 */ 470 #define RTC 471 #define CONFIG_RTC_DS3231 1 472 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 473 474 /* 475 * RapidIO 476 */ 477 #ifdef CONFIG_SYS_SRIO 478 #ifdef CONFIG_SRIO1 479 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 482 #else 483 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 484 #endif 485 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 486 #endif 487 488 #ifdef CONFIG_SRIO2 489 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 492 #else 493 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 494 #endif 495 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 496 #endif 497 #endif 498 499 /* 500 * for slave u-boot IMAGE instored in master memory space, 501 * PHYS must be aligned based on the SIZE 502 */ 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 506 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 507 /* 508 * for slave UCODE and ENV instored in master memory space, 509 * PHYS must be aligned based on the SIZE 510 */ 511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 512 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 513 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 514 515 /* slave core release by master*/ 516 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 517 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 518 519 /* 520 * SRIO_PCIE_BOOT - SLAVE 521 */ 522 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 523 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 524 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 525 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 526 #endif 527 528 /* 529 * eSPI - Enhanced SPI 530 */ 531 #define CONFIG_SF_DEFAULT_SPEED 10000000 532 #define CONFIG_SF_DEFAULT_MODE 0 533 534 /* 535 * MAPLE 536 */ 537 #ifdef CONFIG_PHYS_64BIT 538 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 539 #else 540 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 541 #endif 542 543 /* 544 * General PCI 545 * Memory space is mapped 1-1, but I/O space must start from 0. 546 */ 547 548 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 549 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 550 #ifdef CONFIG_PHYS_64BIT 551 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 552 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 553 #else 554 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 555 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 556 #endif 557 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 558 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 559 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 560 #ifdef CONFIG_PHYS_64BIT 561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 562 #else 563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 564 #endif 565 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 566 567 /* Qman/Bman */ 568 #ifndef CONFIG_NOBQFMAN 569 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 570 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 571 #ifdef CONFIG_PHYS_64BIT 572 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 573 #else 574 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 575 #endif 576 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 577 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 578 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 579 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 580 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 582 CONFIG_SYS_BMAN_CENA_SIZE) 583 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 584 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 585 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 586 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 587 #ifdef CONFIG_PHYS_64BIT 588 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 589 #else 590 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 591 #endif 592 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 593 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 594 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 595 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 596 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 597 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 598 CONFIG_SYS_QMAN_CENA_SIZE) 599 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 600 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 601 602 #define CONFIG_SYS_DPAA_FMAN 603 604 #define CONFIG_SYS_DPAA_RMAN 605 606 /* Default address of microcode for the Linux Fman driver */ 607 #if defined(CONFIG_SPIFLASH) 608 /* 609 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 610 * env, so we got 0x110000. 611 */ 612 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 613 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 614 #elif defined(CONFIG_SDCARD) 615 /* 616 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 617 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 618 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 619 */ 620 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 621 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 622 #elif defined(CONFIG_NAND) 623 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 624 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 625 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 626 /* 627 * Slave has no ucode locally, it can fetch this from remote. When implementing 628 * in two corenet boards, slave's ucode could be stored in master's memory 629 * space, the address can be mapped from slave TLB->slave LAW-> 630 * slave SRIO or PCIE outbound window->master inbound window-> 631 * master LAW->the ucode address in master's memory space. 632 */ 633 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 634 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 635 #else 636 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 637 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 638 #endif 639 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 640 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 641 #endif /* CONFIG_NOBQFMAN */ 642 643 #ifdef CONFIG_SYS_DPAA_FMAN 644 #define CONFIG_FMAN_ENET 645 #define CONFIG_PHYLIB_10G 646 #define CONFIG_PHY_VITESSE 647 #define CONFIG_PHY_TERANETICS 648 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 649 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 650 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 651 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 652 #endif 653 654 #ifdef CONFIG_PCI 655 #define CONFIG_PCI_INDIRECT_BRIDGE 656 657 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 658 #endif /* CONFIG_PCI */ 659 660 #ifdef CONFIG_FMAN_ENET 661 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 662 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 663 664 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 665 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 666 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 667 668 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 669 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 670 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 671 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 672 673 #define CONFIG_MII /* MII PHY management */ 674 #define CONFIG_ETHPRIME "FM1@DTSEC1" 675 #endif 676 677 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 678 679 /* 680 * Environment 681 */ 682 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 683 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 684 685 /* 686 * USB 687 */ 688 #define CONFIG_HAS_FSL_DR_USB 689 690 #ifdef CONFIG_HAS_FSL_DR_USB 691 #ifdef CONFIG_USB_EHCI_HCD 692 #define CONFIG_USB_EHCI_FSL 693 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 694 #endif 695 #endif 696 697 /* 698 * Miscellaneous configurable options 699 */ 700 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 701 702 /* 703 * For booting Linux, the board info and command line data 704 * have to be in the first 64 MB of memory, since this is 705 * the maximum mapped by the Linux kernel during initialization. 706 */ 707 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 708 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 709 710 #ifdef CONFIG_CMD_KGDB 711 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 712 #endif 713 714 /* 715 * Environment Configuration 716 */ 717 #define CONFIG_ROOTPATH "/opt/nfsroot" 718 #define CONFIG_BOOTFILE "uImage" 719 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 720 721 /* default location for tftp and bootm */ 722 #define CONFIG_LOADADDR 1000000 723 724 #define __USB_PHY_TYPE ulpi 725 726 #ifdef CONFIG_ARCH_B4860 727 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 728 "bank_intlv=cs0_cs1;" \ 729 "en_cpc:cpc2;" 730 #else 731 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 732 #endif 733 734 #define CONFIG_EXTRA_ENV_SETTINGS \ 735 HWCONFIG \ 736 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 737 "netdev=eth0\0" \ 738 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 739 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 740 "tftpflash=tftpboot $loadaddr $uboot && " \ 741 "protect off $ubootaddr +$filesize && " \ 742 "erase $ubootaddr +$filesize && " \ 743 "cp.b $loadaddr $ubootaddr $filesize && " \ 744 "protect on $ubootaddr +$filesize && " \ 745 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 746 "consoledev=ttyS0\0" \ 747 "ramdiskaddr=2000000\0" \ 748 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 749 "fdtaddr=1e00000\0" \ 750 "fdtfile=b4860qds/b4860qds.dtb\0" \ 751 "bdev=sda3\0" 752 753 /* For emulation this causes u-boot to jump to the start of the proof point 754 app code automatically */ 755 #define CONFIG_PROOF_POINTS \ 756 "setenv bootargs root=/dev/$bdev rw " \ 757 "console=$consoledev,$baudrate $othbootargs;" \ 758 "cpu 1 release 0x29000000 - - -;" \ 759 "cpu 2 release 0x29000000 - - -;" \ 760 "cpu 3 release 0x29000000 - - -;" \ 761 "cpu 4 release 0x29000000 - - -;" \ 762 "cpu 5 release 0x29000000 - - -;" \ 763 "cpu 6 release 0x29000000 - - -;" \ 764 "cpu 7 release 0x29000000 - - -;" \ 765 "go 0x29000000" 766 767 #define CONFIG_HVBOOT \ 768 "setenv bootargs config-addr=0x60000000; " \ 769 "bootm 0x01000000 - 0x00f00000" 770 771 #define CONFIG_ALU \ 772 "setenv bootargs root=/dev/$bdev rw " \ 773 "console=$consoledev,$baudrate $othbootargs;" \ 774 "cpu 1 release 0x01000000 - - -;" \ 775 "cpu 2 release 0x01000000 - - -;" \ 776 "cpu 3 release 0x01000000 - - -;" \ 777 "cpu 4 release 0x01000000 - - -;" \ 778 "cpu 5 release 0x01000000 - - -;" \ 779 "cpu 6 release 0x01000000 - - -;" \ 780 "cpu 7 release 0x01000000 - - -;" \ 781 "go 0x01000000" 782 783 #define CONFIG_LINUX \ 784 "setenv bootargs root=/dev/ram rw " \ 785 "console=$consoledev,$baudrate $othbootargs;" \ 786 "setenv ramdiskaddr 0x02000000;" \ 787 "setenv fdtaddr 0x01e00000;" \ 788 "setenv loadaddr 0x1000000;" \ 789 "bootm $loadaddr $ramdiskaddr $fdtaddr" 790 791 #define CONFIG_HDBOOT \ 792 "setenv bootargs root=/dev/$bdev rw " \ 793 "console=$consoledev,$baudrate $othbootargs;" \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr - $fdtaddr" 797 798 #define CONFIG_NFSBOOTCOMMAND \ 799 "setenv bootargs root=/dev/nfs rw " \ 800 "nfsroot=$serverip:$rootpath " \ 801 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "tftp $loadaddr $bootfile;" \ 804 "tftp $fdtaddr $fdtfile;" \ 805 "bootm $loadaddr - $fdtaddr" 806 807 #define CONFIG_RAMBOOTCOMMAND \ 808 "setenv bootargs root=/dev/ram rw " \ 809 "console=$consoledev,$baudrate $othbootargs;" \ 810 "tftp $ramdiskaddr $ramdiskfile;" \ 811 "tftp $loadaddr $bootfile;" \ 812 "tftp $fdtaddr $fdtfile;" \ 813 "bootm $loadaddr $ramdiskaddr $fdtaddr" 814 815 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 816 817 #include <asm/fsl_secure_boot.h> 818 819 #endif /* __CONFIG_H */ 820