1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_SYS_GENERIC_BOARD 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* 14 * B4860 QDS board configuration file 15 */ 16 #define CONFIG_B4860QDS 17 #define CONFIG_PHYS_64BIT 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 21 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 22 #ifndef CONFIG_NAND 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #else 26 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 27 #define CONFIG_SPL_ENV_SUPPORT 28 #define CONFIG_SPL_SERIAL_SUPPORT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_SPL_LIBGENERIC_SUPPORT 32 #define CONFIG_SPL_LIBCOMMON_SUPPORT 33 #define CONFIG_SPL_I2C_SUPPORT 34 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 35 #define CONFIG_FSL_LAW /* Use common FSL init code */ 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 #define CONFIG_SPL_NAND_SUPPORT 43 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 44 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 48 #define CONFIG_SPL_NAND_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_SKIP_RELOCATE 51 #define CONFIG_SPL_COMMON_INIT_DDR 52 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 53 #define CONFIG_SYS_NO_FLASH 54 #endif 55 #endif 56 #endif 57 58 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 59 /* Set 1M boot space */ 60 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 61 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 62 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 63 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 /* High Level Configuration Options */ 68 #define CONFIG_BOOKE 69 #define CONFIG_E500 /* BOOKE e500 family */ 70 #define CONFIG_E500MC /* BOOKE e500mc family */ 71 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 72 #define CONFIG_MP /* support multiple processors */ 73 74 #ifndef CONFIG_SYS_TEXT_BASE 75 #define CONFIG_SYS_TEXT_BASE 0xeff40000 76 #endif 77 78 #ifndef CONFIG_RESET_VECTOR_ADDRESS 79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 80 #endif 81 82 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 83 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 84 #define CONFIG_FSL_IFC /* Enable IFC Support */ 85 #define CONFIG_PCI /* Enable PCI/PCIE */ 86 #define CONFIG_PCIE1 /* PCIE controler 1 */ 87 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 88 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 89 90 #ifndef CONFIG_PPC_B4420 91 #define CONFIG_SYS_SRIO 92 #define CONFIG_SRIO1 /* SRIO port 1 */ 93 #define CONFIG_SRIO2 /* SRIO port 2 */ 94 #define CONFIG_SRIO_PCIE_BOOT_MASTER 95 #endif 96 97 #define CONFIG_FSL_LAW /* Use common FSL init code */ 98 99 /* I2C bus multiplexer */ 100 #define I2C_MUX_PCA_ADDR 0x77 101 102 /* VSC Crossbar switches */ 103 #define CONFIG_VSC_CROSSBAR 104 #define I2C_CH_DEFAULT 0x8 105 #define I2C_CH_VSC3316 0xc 106 #define I2C_CH_VSC3308 0xd 107 108 #define VSC3316_TX_ADDRESS 0x70 109 #define VSC3316_RX_ADDRESS 0x71 110 #define VSC3308_TX_ADDRESS 0x02 111 #define VSC3308_RX_ADDRESS 0x03 112 113 /* IDT clock synthesizers */ 114 #define CONFIG_IDT8T49N222A 115 #define I2C_CH_IDT 0x9 116 117 #define IDT_SERDES1_ADDRESS 0x6E 118 #define IDT_SERDES2_ADDRESS 0x6C 119 120 /* Voltage monitor on channel 2*/ 121 #define I2C_MUX_CH_VOL_MONITOR 0xa 122 #define I2C_VOL_MONITOR_ADDR 0x40 123 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 124 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 125 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 126 127 #define CONFIG_ZM7300 128 #define I2C_MUX_CH_DPM 0xa 129 #define I2C_DPM_ADDR 0x28 130 131 #define CONFIG_ENV_OVERWRITE 132 133 #ifdef CONFIG_SYS_NO_FLASH 134 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 135 #define CONFIG_ENV_IS_NOWHERE 136 #endif 137 #else 138 #define CONFIG_FLASH_CFI_DRIVER 139 #define CONFIG_SYS_FLASH_CFI 140 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 141 #endif 142 143 #if defined(CONFIG_SPIFLASH) 144 #define CONFIG_SYS_EXTRA_ENV_RELOC 145 #define CONFIG_ENV_IS_IN_SPI_FLASH 146 #define CONFIG_ENV_SPI_BUS 0 147 #define CONFIG_ENV_SPI_CS 0 148 #define CONFIG_ENV_SPI_MAX_HZ 10000000 149 #define CONFIG_ENV_SPI_MODE 0 150 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 151 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 152 #define CONFIG_ENV_SECT_SIZE 0x10000 153 #elif defined(CONFIG_SDCARD) 154 #define CONFIG_SYS_EXTRA_ENV_RELOC 155 #define CONFIG_ENV_IS_IN_MMC 156 #define CONFIG_SYS_MMC_ENV_DEV 0 157 #define CONFIG_ENV_SIZE 0x2000 158 #define CONFIG_ENV_OFFSET (512 * 1097) 159 #elif defined(CONFIG_NAND) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_NAND 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 165 #define CONFIG_ENV_IS_IN_REMOTE 166 #define CONFIG_ENV_ADDR 0xffe20000 167 #define CONFIG_ENV_SIZE 0x2000 168 #elif defined(CONFIG_ENV_IS_NOWHERE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #else 171 #define CONFIG_ENV_IS_IN_FLASH 172 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 175 #endif 176 177 #ifndef __ASSEMBLY__ 178 unsigned long get_board_sys_clk(void); 179 unsigned long get_board_ddr_clk(void); 180 #endif 181 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 182 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 183 184 /* 185 * These can be toggled for performance analysis, otherwise use default. 186 */ 187 #define CONFIG_SYS_CACHE_STASHING 188 #define CONFIG_BTB /* toggle branch predition */ 189 #define CONFIG_DDR_ECC 190 #ifdef CONFIG_DDR_ECC 191 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 192 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 193 #endif 194 195 #define CONFIG_ENABLE_36BIT_PHYS 196 197 #ifdef CONFIG_PHYS_64BIT 198 #define CONFIG_ADDR_MAP 199 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 200 #endif 201 202 #if 0 203 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 204 #endif 205 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 206 #define CONFIG_SYS_MEMTEST_END 0x00400000 207 #define CONFIG_SYS_ALT_MEMTEST 208 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 209 210 /* 211 * Config the L3 Cache as L3 SRAM 212 */ 213 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 214 #define CONFIG_SYS_L3_SIZE 256 << 10 215 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 216 #ifdef CONFIG_NAND 217 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 218 #endif 219 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 220 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 221 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 222 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 223 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_SYS_DCSRBAR 0xf0000000 226 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 227 #endif 228 229 /* EEPROM */ 230 #define CONFIG_SYS_I2C_EEPROM_NXID 231 #define CONFIG_SYS_EEPROM_BUS_NUM 0 232 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 233 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 236 237 /* 238 * DDR Setup 239 */ 240 #define CONFIG_VERY_BIG_RAM 241 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 242 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 243 244 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 245 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 246 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 247 248 #define CONFIG_DDR_SPD 249 #define CONFIG_SYS_DDR_RAW_TIMING 250 #define CONFIG_SYS_FSL_DDR3 251 #ifndef CONFIG_SPL_BUILD 252 #define CONFIG_FSL_DDR_INTERACTIVE 253 #endif 254 255 #define CONFIG_SYS_SPD_BUS_NUM 0 256 #define SPD_EEPROM_ADDRESS1 0x51 257 #define SPD_EEPROM_ADDRESS2 0x53 258 259 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 260 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 261 262 /* 263 * IFC Definitions 264 */ 265 #define CONFIG_SYS_FLASH_BASE 0xe0000000 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 268 #else 269 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 270 #endif 271 272 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 273 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 274 + 0x8000000) | \ 275 CSPR_PORT_SIZE_16 | \ 276 CSPR_MSEL_NOR | \ 277 CSPR_V) 278 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 279 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 280 CSPR_PORT_SIZE_16 | \ 281 CSPR_MSEL_NOR | \ 282 CSPR_V) 283 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 284 /* NOR Flash Timing Params */ 285 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 286 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 287 FTIM0_NOR_TEADC(0x04) | \ 288 FTIM0_NOR_TEAHC(0x20)) 289 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 290 FTIM1_NOR_TRAD_NOR(0x1A) |\ 291 FTIM1_NOR_TSEQRAD_NOR(0x13)) 292 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 293 FTIM2_NOR_TCH(0x0E) | \ 294 FTIM2_NOR_TWPH(0x0E) | \ 295 FTIM2_NOR_TWP(0x1c)) 296 #define CONFIG_SYS_NOR_FTIM3 0x0 297 298 #define CONFIG_SYS_FLASH_QUIET_TEST 299 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 300 301 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 302 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 303 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 304 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 305 306 #define CONFIG_SYS_FLASH_EMPTY_INFO 307 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 308 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 309 310 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 311 #define CONFIG_FSL_QIXIS_V2 312 #define QIXIS_BASE 0xffdf0000 313 #ifdef CONFIG_PHYS_64BIT 314 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 315 #else 316 #define QIXIS_BASE_PHYS QIXIS_BASE 317 #endif 318 #define QIXIS_LBMAP_SWITCH 0x01 319 #define QIXIS_LBMAP_MASK 0x0f 320 #define QIXIS_LBMAP_SHIFT 0 321 #define QIXIS_LBMAP_DFLTBANK 0x00 322 #define QIXIS_LBMAP_ALTBANK 0x02 323 #define QIXIS_RST_CTL_RESET 0x31 324 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 325 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 326 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 327 328 #define CONFIG_SYS_CSPR3_EXT (0xf) 329 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 330 | CSPR_PORT_SIZE_8 \ 331 | CSPR_MSEL_GPCM \ 332 | CSPR_V) 333 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 334 #define CONFIG_SYS_CSOR3 0x0 335 /* QIXIS Timing parameters for IFC CS3 */ 336 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 337 FTIM0_GPCM_TEADC(0x0e) | \ 338 FTIM0_GPCM_TEAHC(0x0e)) 339 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 340 FTIM1_GPCM_TRAD(0x1f)) 341 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 342 FTIM2_GPCM_TCH(0x8) | \ 343 FTIM2_GPCM_TWP(0x1f)) 344 #define CONFIG_SYS_CS3_FTIM3 0x0 345 346 /* NAND Flash on IFC */ 347 #define CONFIG_NAND_FSL_IFC 348 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 349 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 350 #define CONFIG_SYS_NAND_BASE 0xff800000 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 353 #else 354 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 355 #endif 356 357 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 358 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 359 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 360 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 361 | CSPR_V) 362 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 363 364 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 365 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 366 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 367 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 368 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 369 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 370 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 371 372 #define CONFIG_SYS_NAND_ONFI_DETECTION 373 374 /* ONFI NAND Flash mode0 Timing Params */ 375 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 376 FTIM0_NAND_TWP(0x18) | \ 377 FTIM0_NAND_TWCHT(0x07) | \ 378 FTIM0_NAND_TWH(0x0a)) 379 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 380 FTIM1_NAND_TWBE(0x39) | \ 381 FTIM1_NAND_TRR(0x0e) | \ 382 FTIM1_NAND_TRP(0x18)) 383 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 384 FTIM2_NAND_TREH(0x0a) | \ 385 FTIM2_NAND_TWHRE(0x1e)) 386 #define CONFIG_SYS_NAND_FTIM3 0x0 387 388 #define CONFIG_SYS_NAND_DDR_LAW 11 389 390 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 391 #define CONFIG_SYS_MAX_NAND_DEVICE 1 392 #define CONFIG_MTD_NAND_VERIFY_WRITE 393 #define CONFIG_CMD_NAND 394 395 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 396 397 #if defined(CONFIG_NAND) 398 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 399 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 400 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 401 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 402 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 403 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 404 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 405 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 406 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 407 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 408 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 409 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 410 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 411 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 412 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 413 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 414 #else 415 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 416 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 417 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 424 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 425 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 426 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 427 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 428 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 429 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 430 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 431 #endif 432 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 433 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 434 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 435 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 436 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 437 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 438 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 439 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 440 441 #ifdef CONFIG_SPL_BUILD 442 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 443 #else 444 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 445 #endif 446 447 #if defined(CONFIG_RAMBOOT_PBL) 448 #define CONFIG_SYS_RAMBOOT 449 #endif 450 451 #define CONFIG_BOARD_EARLY_INIT_R 452 #define CONFIG_MISC_INIT_R 453 454 #define CONFIG_HWCONFIG 455 456 /* define to use L1 as initial stack */ 457 #define CONFIG_L1_INIT_RAM 458 #define CONFIG_SYS_INIT_RAM_LOCK 459 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 463 /* The assembler doesn't like typecast */ 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 465 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 466 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 467 #else 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 471 #endif 472 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 473 474 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 475 GENERATED_GBL_DATA_SIZE) 476 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 477 478 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 479 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 480 481 /* Serial Port - controlled on board with jumper J8 482 * open - index 2 483 * shorted - index 1 484 */ 485 #define CONFIG_CONS_INDEX 1 486 #define CONFIG_SYS_NS16550 487 #define CONFIG_SYS_NS16550_SERIAL 488 #define CONFIG_SYS_NS16550_REG_SIZE 1 489 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 490 491 #define CONFIG_SYS_BAUDRATE_TABLE \ 492 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 493 494 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 495 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 496 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 497 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 498 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 499 #ifndef CONFIG_SPL_BUILD 500 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 501 #endif 502 503 504 /* Use the HUSH parser */ 505 #define CONFIG_SYS_HUSH_PARSER 506 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 507 508 /* pass open firmware flat tree */ 509 #define CONFIG_OF_LIBFDT 510 #define CONFIG_OF_BOARD_SETUP 511 #define CONFIG_OF_STDOUT_VIA_ALIAS 512 513 /* new uImage format support */ 514 #define CONFIG_FIT 515 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 516 517 /* I2C */ 518 #define CONFIG_SYS_I2C 519 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 520 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 521 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 523 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 524 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 525 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 526 527 /* 528 * RTC configuration 529 */ 530 #define RTC 531 #define CONFIG_RTC_DS3231 1 532 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 533 534 /* 535 * RapidIO 536 */ 537 #ifdef CONFIG_SYS_SRIO 538 #ifdef CONFIG_SRIO1 539 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 540 #ifdef CONFIG_PHYS_64BIT 541 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 542 #else 543 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 544 #endif 545 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 546 #endif 547 548 #ifdef CONFIG_SRIO2 549 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 550 #ifdef CONFIG_PHYS_64BIT 551 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 552 #else 553 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 554 #endif 555 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 556 #endif 557 #endif 558 559 /* 560 * for slave u-boot IMAGE instored in master memory space, 561 * PHYS must be aligned based on the SIZE 562 */ 563 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 564 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 565 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 566 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 567 /* 568 * for slave UCODE and ENV instored in master memory space, 569 * PHYS must be aligned based on the SIZE 570 */ 571 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 572 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 573 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 574 575 /* slave core release by master*/ 576 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 577 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 578 579 /* 580 * SRIO_PCIE_BOOT - SLAVE 581 */ 582 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 583 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 584 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 585 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 586 #endif 587 588 /* 589 * eSPI - Enhanced SPI 590 */ 591 #define CONFIG_FSL_ESPI 592 #define CONFIG_SPI_FLASH 593 #define CONFIG_SPI_FLASH_SST 594 #define CONFIG_CMD_SF 595 #define CONFIG_SF_DEFAULT_SPEED 10000000 596 #define CONFIG_SF_DEFAULT_MODE 0 597 598 /* 599 * MAPLE 600 */ 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 603 #else 604 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 605 #endif 606 607 /* 608 * General PCI 609 * Memory space is mapped 1-1, but I/O space must start from 0. 610 */ 611 612 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 613 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 616 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 617 #else 618 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 619 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 620 #endif 621 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 622 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 623 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 624 #ifdef CONFIG_PHYS_64BIT 625 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 626 #else 627 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 628 #endif 629 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 630 631 /* Qman/Bman */ 632 #ifndef CONFIG_NOBQFMAN 633 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 634 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 635 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 636 #ifdef CONFIG_PHYS_64BIT 637 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 638 #else 639 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 640 #endif 641 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 642 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 643 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 644 #ifdef CONFIG_PHYS_64BIT 645 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 646 #else 647 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 648 #endif 649 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 650 651 #define CONFIG_SYS_DPAA_FMAN 652 653 #define CONFIG_SYS_DPAA_RMAN 654 655 /* Default address of microcode for the Linux Fman driver */ 656 #if defined(CONFIG_SPIFLASH) 657 /* 658 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 659 * env, so we got 0x110000. 660 */ 661 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 662 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 663 #elif defined(CONFIG_SDCARD) 664 /* 665 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 666 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 667 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 668 */ 669 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 670 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 671 #elif defined(CONFIG_NAND) 672 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 673 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 674 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 675 /* 676 * Slave has no ucode locally, it can fetch this from remote. When implementing 677 * in two corenet boards, slave's ucode could be stored in master's memory 678 * space, the address can be mapped from slave TLB->slave LAW-> 679 * slave SRIO or PCIE outbound window->master inbound window-> 680 * master LAW->the ucode address in master's memory space. 681 */ 682 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 683 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 684 #else 685 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 686 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 687 #endif 688 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 689 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 690 #endif /* CONFIG_NOBQFMAN */ 691 692 #ifdef CONFIG_SYS_DPAA_FMAN 693 #define CONFIG_FMAN_ENET 694 #define CONFIG_PHYLIB_10G 695 #define CONFIG_PHY_VITESSE 696 #define CONFIG_PHY_TERANETICS 697 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 698 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 699 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 700 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 701 #endif 702 703 #ifdef CONFIG_PCI 704 #define CONFIG_PCI_INDIRECT_BRIDGE 705 #define CONFIG_NET_MULTI 706 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 707 #define CONFIG_E1000 708 709 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 710 #define CONFIG_DOS_PARTITION 711 #endif /* CONFIG_PCI */ 712 713 #ifdef CONFIG_FMAN_ENET 714 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 715 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 716 717 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 718 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 719 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 720 721 722 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 723 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 724 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 725 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 726 727 #define CONFIG_MII /* MII PHY management */ 728 #define CONFIG_ETHPRIME "FM1@DTSEC1" 729 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 730 #endif 731 732 /* 733 * Environment 734 */ 735 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 736 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 737 738 /* 739 * Command line configuration. 740 */ 741 #include <config_cmd_default.h> 742 743 #define CONFIG_CMD_DATE 744 #define CONFIG_CMD_DHCP 745 #define CONFIG_CMD_EEPROM 746 #define CONFIG_CMD_ELF 747 #define CONFIG_CMD_ERRATA 748 #define CONFIG_CMD_GREPENV 749 #define CONFIG_CMD_IRQ 750 #define CONFIG_CMD_I2C 751 #define CONFIG_CMD_MII 752 #define CONFIG_CMD_PING 753 #define CONFIG_CMD_REGINFO 754 #define CONFIG_CMD_SETEXPR 755 756 #ifdef CONFIG_PCI 757 #define CONFIG_CMD_PCI 758 #define CONFIG_CMD_NET 759 #endif 760 761 /* 762 * USB 763 */ 764 #define CONFIG_HAS_FSL_DR_USB 765 766 #ifdef CONFIG_HAS_FSL_DR_USB 767 #define CONFIG_USB_EHCI 768 769 #ifdef CONFIG_USB_EHCI 770 #define CONFIG_CMD_USB 771 #define CONFIG_USB_STORAGE 772 #define CONFIG_USB_EHCI_FSL 773 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 774 #define CONFIG_CMD_EXT2 775 #endif 776 #endif 777 778 /* 779 * Miscellaneous configurable options 780 */ 781 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 782 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 783 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 784 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 785 #ifdef CONFIG_CMD_KGDB 786 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 787 #else 788 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 789 #endif 790 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 791 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 792 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 793 794 /* 795 * For booting Linux, the board info and command line data 796 * have to be in the first 64 MB of memory, since this is 797 * the maximum mapped by the Linux kernel during initialization. 798 */ 799 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 801 802 #ifdef CONFIG_CMD_KGDB 803 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 804 #endif 805 806 /* 807 * Environment Configuration 808 */ 809 #define CONFIG_ROOTPATH "/opt/nfsroot" 810 #define CONFIG_BOOTFILE "uImage" 811 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 812 813 /* default location for tftp and bootm */ 814 #define CONFIG_LOADADDR 1000000 815 816 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 817 818 #define CONFIG_BAUDRATE 115200 819 820 #define __USB_PHY_TYPE ulpi 821 822 #define CONFIG_EXTRA_ENV_SETTINGS \ 823 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 824 "bank_intlv=cs0_cs1;" \ 825 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 826 "netdev=eth0\0" \ 827 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 828 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 829 "tftpflash=tftpboot $loadaddr $uboot && " \ 830 "protect off $ubootaddr +$filesize && " \ 831 "erase $ubootaddr +$filesize && " \ 832 "cp.b $loadaddr $ubootaddr $filesize && " \ 833 "protect on $ubootaddr +$filesize && " \ 834 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 835 "consoledev=ttyS0\0" \ 836 "ramdiskaddr=2000000\0" \ 837 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 838 "fdtaddr=c00000\0" \ 839 "fdtfile=b4860qds/b4860qds.dtb\0" \ 840 "bdev=sda3\0" 841 842 /* For emulation this causes u-boot to jump to the start of the proof point 843 app code automatically */ 844 #define CONFIG_PROOF_POINTS \ 845 "setenv bootargs root=/dev/$bdev rw " \ 846 "console=$consoledev,$baudrate $othbootargs;" \ 847 "cpu 1 release 0x29000000 - - -;" \ 848 "cpu 2 release 0x29000000 - - -;" \ 849 "cpu 3 release 0x29000000 - - -;" \ 850 "cpu 4 release 0x29000000 - - -;" \ 851 "cpu 5 release 0x29000000 - - -;" \ 852 "cpu 6 release 0x29000000 - - -;" \ 853 "cpu 7 release 0x29000000 - - -;" \ 854 "go 0x29000000" 855 856 #define CONFIG_HVBOOT \ 857 "setenv bootargs config-addr=0x60000000; " \ 858 "bootm 0x01000000 - 0x00f00000" 859 860 #define CONFIG_ALU \ 861 "setenv bootargs root=/dev/$bdev rw " \ 862 "console=$consoledev,$baudrate $othbootargs;" \ 863 "cpu 1 release 0x01000000 - - -;" \ 864 "cpu 2 release 0x01000000 - - -;" \ 865 "cpu 3 release 0x01000000 - - -;" \ 866 "cpu 4 release 0x01000000 - - -;" \ 867 "cpu 5 release 0x01000000 - - -;" \ 868 "cpu 6 release 0x01000000 - - -;" \ 869 "cpu 7 release 0x01000000 - - -;" \ 870 "go 0x01000000" 871 872 #define CONFIG_LINUX \ 873 "setenv bootargs root=/dev/ram rw " \ 874 "console=$consoledev,$baudrate $othbootargs;" \ 875 "setenv ramdiskaddr 0x02000000;" \ 876 "setenv fdtaddr 0x00c00000;" \ 877 "setenv loadaddr 0x1000000;" \ 878 "bootm $loadaddr $ramdiskaddr $fdtaddr" 879 880 #define CONFIG_HDBOOT \ 881 "setenv bootargs root=/dev/$bdev rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "tftp $loadaddr $bootfile;" \ 884 "tftp $fdtaddr $fdtfile;" \ 885 "bootm $loadaddr - $fdtaddr" 886 887 #define CONFIG_NFSBOOTCOMMAND \ 888 "setenv bootargs root=/dev/nfs rw " \ 889 "nfsroot=$serverip:$rootpath " \ 890 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 891 "console=$consoledev,$baudrate $othbootargs;" \ 892 "tftp $loadaddr $bootfile;" \ 893 "tftp $fdtaddr $fdtfile;" \ 894 "bootm $loadaddr - $fdtaddr" 895 896 #define CONFIG_RAMBOOTCOMMAND \ 897 "setenv bootargs root=/dev/ram rw " \ 898 "console=$consoledev,$baudrate $othbootargs;" \ 899 "tftp $ramdiskaddr $ramdiskfile;" \ 900 "tftp $loadaddr $bootfile;" \ 901 "tftp $fdtaddr $fdtfile;" \ 902 "bootm $loadaddr $ramdiskaddr $fdtaddr" 903 904 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 905 906 #include <asm/fsl_secure_boot.h> 907 908 #endif /* __CONFIG_H */ 909