1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * B4860 QDS board configuration file 11 */ 12 #ifdef CONFIG_RAMBOOT_PBL 13 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 14 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 15 #ifndef CONFIG_NAND 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #else 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 21 #define CONFIG_SPL_PAD_TO 0x40000 22 #define CONFIG_SPL_MAX_SIZE 0x28000 23 #define RESET_VECTOR_OFFSET 0x27FFC 24 #define BOOT_PAGE_OFFSET 0x27000 25 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 26 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 27 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 28 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 29 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 30 #define CONFIG_SPL_NAND_BOOT 31 #ifdef CONFIG_SPL_BUILD 32 #define CONFIG_SPL_SKIP_RELOCATE 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 56 #define CONFIG_PCIE1 /* PCIE controller 1 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #ifndef CONFIG_ARCH_B4420 61 #define CONFIG_SYS_SRIO 62 #define CONFIG_SRIO1 /* SRIO port 1 */ 63 #define CONFIG_SRIO2 /* SRIO port 2 */ 64 #define CONFIG_SRIO_PCIE_BOOT_MASTER 65 #endif 66 67 /* I2C bus multiplexer */ 68 #define I2C_MUX_PCA_ADDR 0x77 69 70 /* VSC Crossbar switches */ 71 #define CONFIG_VSC_CROSSBAR 72 #define I2C_CH_DEFAULT 0x8 73 #define I2C_CH_VSC3316 0xc 74 #define I2C_CH_VSC3308 0xd 75 76 #define VSC3316_TX_ADDRESS 0x70 77 #define VSC3316_RX_ADDRESS 0x71 78 #define VSC3308_TX_ADDRESS 0x02 79 #define VSC3308_RX_ADDRESS 0x03 80 81 /* IDT clock synthesizers */ 82 #define CONFIG_IDT8T49N222A 83 #define I2C_CH_IDT 0x9 84 85 #define IDT_SERDES1_ADDRESS 0x6E 86 #define IDT_SERDES2_ADDRESS 0x6C 87 88 /* Voltage monitor on channel 2*/ 89 #define I2C_MUX_CH_VOL_MONITOR 0xa 90 #define I2C_VOL_MONITOR_ADDR 0x40 91 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 92 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 93 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 94 95 #define CONFIG_ZM7300 96 #define I2C_MUX_CH_DPM 0xa 97 #define I2C_DPM_ADDR 0x28 98 99 #define CONFIG_ENV_OVERWRITE 100 101 #ifndef CONFIG_MTD_NOR_FLASH 102 #else 103 #define CONFIG_FLASH_CFI_DRIVER 104 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 106 #endif 107 108 #if defined(CONFIG_SPIFLASH) 109 #define CONFIG_SYS_EXTRA_ENV_RELOC 110 #define CONFIG_ENV_SPI_BUS 0 111 #define CONFIG_ENV_SPI_CS 0 112 #define CONFIG_ENV_SPI_MAX_HZ 10000000 113 #define CONFIG_ENV_SPI_MODE 0 114 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 115 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 116 #define CONFIG_ENV_SECT_SIZE 0x10000 117 #elif defined(CONFIG_SDCARD) 118 #define CONFIG_SYS_EXTRA_ENV_RELOC 119 #define CONFIG_SYS_MMC_ENV_DEV 0 120 #define CONFIG_ENV_SIZE 0x2000 121 #define CONFIG_ENV_OFFSET (512 * 1097) 122 #elif defined(CONFIG_NAND) 123 #define CONFIG_SYS_EXTRA_ENV_RELOC 124 #define CONFIG_ENV_SIZE 0x2000 125 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 126 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 127 #define CONFIG_ENV_ADDR 0xffe20000 128 #define CONFIG_ENV_SIZE 0x2000 129 #elif defined(CONFIG_ENV_IS_NOWHERE) 130 #define CONFIG_ENV_SIZE 0x2000 131 #else 132 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 133 #define CONFIG_ENV_SIZE 0x2000 134 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 135 #endif 136 137 #ifndef __ASSEMBLY__ 138 unsigned long get_board_sys_clk(void); 139 unsigned long get_board_ddr_clk(void); 140 #endif 141 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 142 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 143 144 /* 145 * These can be toggled for performance analysis, otherwise use default. 146 */ 147 #define CONFIG_SYS_CACHE_STASHING 148 #define CONFIG_BTB /* toggle branch predition */ 149 #define CONFIG_DDR_ECC 150 #ifdef CONFIG_DDR_ECC 151 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 152 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 153 #endif 154 155 #define CONFIG_ENABLE_36BIT_PHYS 156 157 #ifdef CONFIG_PHYS_64BIT 158 #define CONFIG_ADDR_MAP 159 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 160 #endif 161 162 #if 0 163 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 164 #endif 165 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 166 #define CONFIG_SYS_MEMTEST_END 0x00400000 167 168 /* 169 * Config the L3 Cache as L3 SRAM 170 */ 171 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 172 #define CONFIG_SYS_L3_SIZE 256 << 10 173 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 174 #ifdef CONFIG_NAND 175 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 176 #endif 177 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 178 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 179 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 180 181 #ifdef CONFIG_PHYS_64BIT 182 #define CONFIG_SYS_DCSRBAR 0xf0000000 183 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 184 #endif 185 186 /* EEPROM */ 187 #define CONFIG_ID_EEPROM 188 #define CONFIG_SYS_I2C_EEPROM_NXID 189 #define CONFIG_SYS_EEPROM_BUS_NUM 0 190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 191 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 194 195 /* 196 * DDR Setup 197 */ 198 #define CONFIG_VERY_BIG_RAM 199 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 200 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 201 202 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 203 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 204 205 #define CONFIG_DDR_SPD 206 #define CONFIG_SYS_DDR_RAW_TIMING 207 #ifndef CONFIG_SPL_BUILD 208 #define CONFIG_FSL_DDR_INTERACTIVE 209 #endif 210 211 #define CONFIG_SYS_SPD_BUS_NUM 0 212 #define SPD_EEPROM_ADDRESS1 0x51 213 #define SPD_EEPROM_ADDRESS2 0x53 214 215 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 216 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 217 218 /* 219 * IFC Definitions 220 */ 221 #define CONFIG_SYS_FLASH_BASE 0xe0000000 222 #ifdef CONFIG_PHYS_64BIT 223 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 224 #else 225 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 226 #endif 227 228 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 229 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 230 + 0x8000000) | \ 231 CSPR_PORT_SIZE_16 | \ 232 CSPR_MSEL_NOR | \ 233 CSPR_V) 234 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 235 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 240 /* NOR Flash Timing Params */ 241 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 242 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 243 FTIM0_NOR_TEADC(0x04) | \ 244 FTIM0_NOR_TEAHC(0x20)) 245 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 246 FTIM1_NOR_TRAD_NOR(0x1A) |\ 247 FTIM1_NOR_TSEQRAD_NOR(0x13)) 248 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 249 FTIM2_NOR_TCH(0x0E) | \ 250 FTIM2_NOR_TWPH(0x0E) | \ 251 FTIM2_NOR_TWP(0x1c)) 252 #define CONFIG_SYS_NOR_FTIM3 0x0 253 254 #define CONFIG_SYS_FLASH_QUIET_TEST 255 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 256 257 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 258 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 259 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 260 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 261 262 #define CONFIG_SYS_FLASH_EMPTY_INFO 263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 264 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 265 266 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 267 #define CONFIG_FSL_QIXIS_V2 268 #define QIXIS_BASE 0xffdf0000 269 #ifdef CONFIG_PHYS_64BIT 270 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 271 #else 272 #define QIXIS_BASE_PHYS QIXIS_BASE 273 #endif 274 #define QIXIS_LBMAP_SWITCH 0x01 275 #define QIXIS_LBMAP_MASK 0x0f 276 #define QIXIS_LBMAP_SHIFT 0 277 #define QIXIS_LBMAP_DFLTBANK 0x00 278 #define QIXIS_LBMAP_ALTBANK 0x02 279 #define QIXIS_RST_CTL_RESET 0x31 280 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 281 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 282 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 283 284 #define CONFIG_SYS_CSPR3_EXT (0xf) 285 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 286 | CSPR_PORT_SIZE_8 \ 287 | CSPR_MSEL_GPCM \ 288 | CSPR_V) 289 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 290 #define CONFIG_SYS_CSOR3 0x0 291 /* QIXIS Timing parameters for IFC CS3 */ 292 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 293 FTIM0_GPCM_TEADC(0x0e) | \ 294 FTIM0_GPCM_TEAHC(0x0e)) 295 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 296 FTIM1_GPCM_TRAD(0x1f)) 297 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 298 FTIM2_GPCM_TCH(0x8) | \ 299 FTIM2_GPCM_TWP(0x1f)) 300 #define CONFIG_SYS_CS3_FTIM3 0x0 301 302 /* NAND Flash on IFC */ 303 #define CONFIG_NAND_FSL_IFC 304 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 305 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 306 #define CONFIG_SYS_NAND_BASE 0xff800000 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 309 #else 310 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 311 #endif 312 313 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 314 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 315 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 316 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 317 | CSPR_V) 318 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 319 320 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 321 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 322 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 323 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 324 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 325 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 326 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 327 328 #define CONFIG_SYS_NAND_ONFI_DETECTION 329 330 /* ONFI NAND Flash mode0 Timing Params */ 331 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 332 FTIM0_NAND_TWP(0x18) | \ 333 FTIM0_NAND_TWCHT(0x07) | \ 334 FTIM0_NAND_TWH(0x0a)) 335 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 336 FTIM1_NAND_TWBE(0x39) | \ 337 FTIM1_NAND_TRR(0x0e) | \ 338 FTIM1_NAND_TRP(0x18)) 339 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 340 FTIM2_NAND_TREH(0x0a) | \ 341 FTIM2_NAND_TWHRE(0x1e)) 342 #define CONFIG_SYS_NAND_FTIM3 0x0 343 344 #define CONFIG_SYS_NAND_DDR_LAW 11 345 346 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 347 #define CONFIG_SYS_MAX_NAND_DEVICE 1 348 349 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 350 351 #if defined(CONFIG_NAND) 352 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 353 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 354 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 355 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 356 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 357 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 358 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 359 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 360 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 361 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 362 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 363 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 364 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 365 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 366 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 367 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 368 #else 369 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 370 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 371 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 372 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 373 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 374 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 375 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 376 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 377 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 378 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 379 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 380 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 381 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 382 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 383 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 384 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 385 #endif 386 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 387 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 388 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 389 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 390 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 391 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 392 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 393 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 394 395 #ifdef CONFIG_SPL_BUILD 396 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 397 #else 398 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 399 #endif 400 401 #if defined(CONFIG_RAMBOOT_PBL) 402 #define CONFIG_SYS_RAMBOOT 403 #endif 404 405 #define CONFIG_HWCONFIG 406 407 /* define to use L1 as initial stack */ 408 #define CONFIG_L1_INIT_RAM 409 #define CONFIG_SYS_INIT_RAM_LOCK 410 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 411 #ifdef CONFIG_PHYS_64BIT 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 414 /* The assembler doesn't like typecast */ 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 416 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 417 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 418 #else 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 422 #endif 423 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 424 425 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 426 GENERATED_GBL_DATA_SIZE) 427 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 428 429 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 430 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 431 432 /* Serial Port - controlled on board with jumper J8 433 * open - index 2 434 * shorted - index 1 435 */ 436 #define CONFIG_SYS_NS16550_SERIAL 437 #define CONFIG_SYS_NS16550_REG_SIZE 1 438 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 439 440 #define CONFIG_SYS_BAUDRATE_TABLE \ 441 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 442 443 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 444 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 445 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 446 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 447 448 /* I2C */ 449 #define CONFIG_SYS_I2C 450 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 451 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 452 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 454 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 455 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 456 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 457 458 /* 459 * RTC configuration 460 */ 461 #define RTC 462 #define CONFIG_RTC_DS3231 1 463 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 464 465 /* 466 * RapidIO 467 */ 468 #ifdef CONFIG_SYS_SRIO 469 #ifdef CONFIG_SRIO1 470 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 473 #else 474 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 475 #endif 476 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 477 #endif 478 479 #ifdef CONFIG_SRIO2 480 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 483 #else 484 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 485 #endif 486 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 487 #endif 488 #endif 489 490 /* 491 * for slave u-boot IMAGE instored in master memory space, 492 * PHYS must be aligned based on the SIZE 493 */ 494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 496 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 498 /* 499 * for slave UCODE and ENV instored in master memory space, 500 * PHYS must be aligned based on the SIZE 501 */ 502 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 503 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 504 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 505 506 /* slave core release by master*/ 507 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 508 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 509 510 /* 511 * SRIO_PCIE_BOOT - SLAVE 512 */ 513 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 514 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 515 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 516 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 517 #endif 518 519 /* 520 * eSPI - Enhanced SPI 521 */ 522 #define CONFIG_SF_DEFAULT_SPEED 10000000 523 #define CONFIG_SF_DEFAULT_MODE 0 524 525 /* 526 * MAPLE 527 */ 528 #ifdef CONFIG_PHYS_64BIT 529 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 530 #else 531 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 532 #endif 533 534 /* 535 * General PCI 536 * Memory space is mapped 1-1, but I/O space must start from 0. 537 */ 538 539 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 540 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 541 #ifdef CONFIG_PHYS_64BIT 542 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 543 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 544 #else 545 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 546 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 547 #endif 548 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 549 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 550 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 551 #ifdef CONFIG_PHYS_64BIT 552 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 553 #else 554 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 555 #endif 556 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 557 558 /* Qman/Bman */ 559 #ifndef CONFIG_NOBQFMAN 560 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 561 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 562 #ifdef CONFIG_PHYS_64BIT 563 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 564 #else 565 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 566 #endif 567 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 568 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 569 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 570 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 571 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 573 CONFIG_SYS_BMAN_CENA_SIZE) 574 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 575 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 576 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 577 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 580 #else 581 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 582 #endif 583 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 584 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 585 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 586 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 587 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 588 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 589 CONFIG_SYS_QMAN_CENA_SIZE) 590 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 591 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 592 593 #define CONFIG_SYS_DPAA_FMAN 594 595 #define CONFIG_SYS_DPAA_RMAN 596 597 /* Default address of microcode for the Linux Fman driver */ 598 #if defined(CONFIG_SPIFLASH) 599 /* 600 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 601 * env, so we got 0x110000. 602 */ 603 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 604 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 605 #elif defined(CONFIG_SDCARD) 606 /* 607 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 608 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 609 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 610 */ 611 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 612 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 613 #elif defined(CONFIG_NAND) 614 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 615 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 617 /* 618 * Slave has no ucode locally, it can fetch this from remote. When implementing 619 * in two corenet boards, slave's ucode could be stored in master's memory 620 * space, the address can be mapped from slave TLB->slave LAW-> 621 * slave SRIO or PCIE outbound window->master inbound window-> 622 * master LAW->the ucode address in master's memory space. 623 */ 624 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 625 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 626 #else 627 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 628 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 629 #endif 630 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 631 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 632 #endif /* CONFIG_NOBQFMAN */ 633 634 #ifdef CONFIG_SYS_DPAA_FMAN 635 #define CONFIG_FMAN_ENET 636 #define CONFIG_PHYLIB_10G 637 #define CONFIG_PHY_VITESSE 638 #define CONFIG_PHY_TERANETICS 639 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 640 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 641 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 642 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 643 #endif 644 645 #ifdef CONFIG_PCI 646 #define CONFIG_PCI_INDIRECT_BRIDGE 647 648 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 649 #endif /* CONFIG_PCI */ 650 651 #ifdef CONFIG_FMAN_ENET 652 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 653 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 654 655 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 656 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 657 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 658 659 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 660 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 661 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 662 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 663 664 #define CONFIG_ETHPRIME "FM1@DTSEC1" 665 #endif 666 667 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 668 669 /* 670 * Environment 671 */ 672 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 673 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 674 675 /* 676 * USB 677 */ 678 #define CONFIG_HAS_FSL_DR_USB 679 680 #ifdef CONFIG_HAS_FSL_DR_USB 681 #ifdef CONFIG_USB_EHCI_HCD 682 #define CONFIG_USB_EHCI_FSL 683 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 684 #endif 685 #endif 686 687 /* 688 * Miscellaneous configurable options 689 */ 690 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 691 692 /* 693 * For booting Linux, the board info and command line data 694 * have to be in the first 64 MB of memory, since this is 695 * the maximum mapped by the Linux kernel during initialization. 696 */ 697 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 698 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 699 700 #ifdef CONFIG_CMD_KGDB 701 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 702 #endif 703 704 /* 705 * Environment Configuration 706 */ 707 #define CONFIG_ROOTPATH "/opt/nfsroot" 708 #define CONFIG_BOOTFILE "uImage" 709 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 710 711 /* default location for tftp and bootm */ 712 #define CONFIG_LOADADDR 1000000 713 714 #define __USB_PHY_TYPE ulpi 715 716 #ifdef CONFIG_ARCH_B4860 717 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 718 "bank_intlv=cs0_cs1;" \ 719 "en_cpc:cpc2;" 720 #else 721 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 722 #endif 723 724 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 HWCONFIG \ 726 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 727 "netdev=eth0\0" \ 728 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 729 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 730 "tftpflash=tftpboot $loadaddr $uboot && " \ 731 "protect off $ubootaddr +$filesize && " \ 732 "erase $ubootaddr +$filesize && " \ 733 "cp.b $loadaddr $ubootaddr $filesize && " \ 734 "protect on $ubootaddr +$filesize && " \ 735 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 736 "consoledev=ttyS0\0" \ 737 "ramdiskaddr=2000000\0" \ 738 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 739 "fdtaddr=1e00000\0" \ 740 "fdtfile=b4860qds/b4860qds.dtb\0" \ 741 "bdev=sda3\0" 742 743 /* For emulation this causes u-boot to jump to the start of the proof point 744 app code automatically */ 745 #define CONFIG_PROOF_POINTS \ 746 "setenv bootargs root=/dev/$bdev rw " \ 747 "console=$consoledev,$baudrate $othbootargs;" \ 748 "cpu 1 release 0x29000000 - - -;" \ 749 "cpu 2 release 0x29000000 - - -;" \ 750 "cpu 3 release 0x29000000 - - -;" \ 751 "cpu 4 release 0x29000000 - - -;" \ 752 "cpu 5 release 0x29000000 - - -;" \ 753 "cpu 6 release 0x29000000 - - -;" \ 754 "cpu 7 release 0x29000000 - - -;" \ 755 "go 0x29000000" 756 757 #define CONFIG_HVBOOT \ 758 "setenv bootargs config-addr=0x60000000; " \ 759 "bootm 0x01000000 - 0x00f00000" 760 761 #define CONFIG_ALU \ 762 "setenv bootargs root=/dev/$bdev rw " \ 763 "console=$consoledev,$baudrate $othbootargs;" \ 764 "cpu 1 release 0x01000000 - - -;" \ 765 "cpu 2 release 0x01000000 - - -;" \ 766 "cpu 3 release 0x01000000 - - -;" \ 767 "cpu 4 release 0x01000000 - - -;" \ 768 "cpu 5 release 0x01000000 - - -;" \ 769 "cpu 6 release 0x01000000 - - -;" \ 770 "cpu 7 release 0x01000000 - - -;" \ 771 "go 0x01000000" 772 773 #define CONFIG_LINUX \ 774 "setenv bootargs root=/dev/ram rw " \ 775 "console=$consoledev,$baudrate $othbootargs;" \ 776 "setenv ramdiskaddr 0x02000000;" \ 777 "setenv fdtaddr 0x01e00000;" \ 778 "setenv loadaddr 0x1000000;" \ 779 "bootm $loadaddr $ramdiskaddr $fdtaddr" 780 781 #define CONFIG_HDBOOT \ 782 "setenv bootargs root=/dev/$bdev rw " \ 783 "console=$consoledev,$baudrate $othbootargs;" \ 784 "tftp $loadaddr $bootfile;" \ 785 "tftp $fdtaddr $fdtfile;" \ 786 "bootm $loadaddr - $fdtaddr" 787 788 #define CONFIG_NFSBOOTCOMMAND \ 789 "setenv bootargs root=/dev/nfs rw " \ 790 "nfsroot=$serverip:$rootpath " \ 791 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "tftp $loadaddr $bootfile;" \ 794 "tftp $fdtaddr $fdtfile;" \ 795 "bootm $loadaddr - $fdtaddr" 796 797 #define CONFIG_RAMBOOTCOMMAND \ 798 "setenv bootargs root=/dev/ram rw " \ 799 "console=$consoledev,$baudrate $othbootargs;" \ 800 "tftp $ramdiskaddr $ramdiskfile;" \ 801 "tftp $loadaddr $bootfile;" \ 802 "tftp $fdtaddr $fdtfile;" \ 803 "bootm $loadaddr $ramdiskaddr $fdtaddr" 804 805 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 806 807 #include <asm/fsl_secure_boot.h> 808 809 #endif /* __CONFIG_H */ 810