1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #define CONFIG_B4860QDS 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #define CONFIG_SYS_NO_FLASH 28 #endif 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 32 #define CONFIG_E500 /* BOOKE e500 family */ 33 #define CONFIG_E500MC /* BOOKE e500mc family */ 34 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 35 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 36 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 37 #define CONFIG_MP /* support multiple processors */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xeff80000 41 #endif 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 49 #define CONFIG_FSL_IFC /* Enable IFC Support */ 50 #define CONFIG_PCI /* Enable PCI/PCIE */ 51 #define CONFIG_PCIE1 /* PCIE controler 1 */ 52 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 53 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 54 55 #ifndef CONFIG_PPC_B4420 56 #define CONFIG_SYS_SRIO 57 #define CONFIG_SRIO1 /* SRIO port 1 */ 58 #define CONFIG_SRIO2 /* SRIO port 2 */ 59 #define CONFIG_SRIO_PCIE_BOOT_MASTER 60 #endif 61 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 64 /* I2C bus multiplexer */ 65 #define I2C_MUX_PCA_ADDR 0x77 66 67 /* VSC Crossbar switches */ 68 #define CONFIG_VSC_CROSSBAR 69 #define I2C_CH_DEFAULT 0x8 70 #define I2C_CH_VSC3316 0xc 71 #define I2C_CH_VSC3308 0xd 72 73 #define VSC3316_TX_ADDRESS 0x70 74 #define VSC3316_RX_ADDRESS 0x71 75 #define VSC3308_TX_ADDRESS 0x02 76 #define VSC3308_RX_ADDRESS 0x03 77 78 #define CONFIG_ENV_OVERWRITE 79 80 #ifdef CONFIG_SYS_NO_FLASH 81 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 82 #define CONFIG_ENV_IS_NOWHERE 83 #endif 84 #else 85 #define CONFIG_FLASH_CFI_DRIVER 86 #define CONFIG_SYS_FLASH_CFI 87 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 88 #endif 89 90 #if defined(CONFIG_SPIFLASH) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_SPI_FLASH 93 #define CONFIG_ENV_SPI_BUS 0 94 #define CONFIG_ENV_SPI_CS 0 95 #define CONFIG_ENV_SPI_MAX_HZ 10000000 96 #define CONFIG_ENV_SPI_MODE 0 97 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 98 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 99 #define CONFIG_ENV_SECT_SIZE 0x10000 100 #elif defined(CONFIG_SDCARD) 101 #define CONFIG_SYS_EXTRA_ENV_RELOC 102 #define CONFIG_ENV_IS_IN_MMC 103 #define CONFIG_SYS_MMC_ENV_DEV 0 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_OFFSET (512 * 1097) 106 #elif defined(CONFIG_NAND) 107 #define CONFIG_SYS_EXTRA_ENV_RELOC 108 #define CONFIG_ENV_IS_IN_NAND 109 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 110 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 111 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 112 #define CONFIG_ENV_IS_IN_REMOTE 113 #define CONFIG_ENV_ADDR 0xffe20000 114 #define CONFIG_ENV_SIZE 0x2000 115 #elif defined(CONFIG_ENV_IS_NOWHERE) 116 #define CONFIG_ENV_SIZE 0x2000 117 #else 118 #define CONFIG_ENV_IS_IN_FLASH 119 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 120 #define CONFIG_ENV_SIZE 0x2000 121 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 122 #endif 123 124 #ifndef __ASSEMBLY__ 125 unsigned long get_board_sys_clk(void); 126 unsigned long get_board_ddr_clk(void); 127 #endif 128 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 129 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 130 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_SYS_CACHE_STASHING 135 #define CONFIG_BTB /* toggle branch predition */ 136 #define CONFIG_DDR_ECC 137 #ifdef CONFIG_DDR_ECC 138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 140 #endif 141 142 #define CONFIG_ENABLE_36BIT_PHYS 143 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_ADDR_MAP 146 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 147 #endif 148 149 #if 0 150 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 151 #endif 152 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 153 #define CONFIG_SYS_MEMTEST_END 0x00400000 154 #define CONFIG_SYS_ALT_MEMTEST 155 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 156 157 /* 158 * Config the L3 Cache as L3 SRAM 159 */ 160 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 161 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_DCSRBAR 0xf0000000 164 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 165 #endif 166 167 /* EEPROM */ 168 #define CONFIG_SYS_I2C_EEPROM_NXID 169 #define CONFIG_SYS_EEPROM_BUS_NUM 0 170 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 173 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 174 175 /* 176 * DDR Setup 177 */ 178 #define CONFIG_VERY_BIG_RAM 179 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 180 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 181 182 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 183 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 184 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 185 186 #define CONFIG_DDR_SPD 187 #define CONFIG_SYS_DDR_RAW_TIMING 188 #define CONFIG_FSL_DDR3 189 #define CONFIG_FSL_DDR_INTERACTIVE 190 191 #define CONFIG_SYS_SPD_BUS_NUM 0 192 #define SPD_EEPROM_ADDRESS1 0x51 193 #define SPD_EEPROM_ADDRESS2 0x53 194 195 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 196 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 197 198 /* 199 * IFC Definitions 200 */ 201 #define CONFIG_SYS_FLASH_BASE 0xe0000000 202 #ifdef CONFIG_PHYS_64BIT 203 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 204 #else 205 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 206 #endif 207 208 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 209 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 210 + 0x8000000) | \ 211 CSPR_PORT_SIZE_16 | \ 212 CSPR_MSEL_NOR | \ 213 CSPR_V) 214 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 215 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 216 CSPR_PORT_SIZE_16 | \ 217 CSPR_MSEL_NOR | \ 218 CSPR_V) 219 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 220 /* NOR Flash Timing Params */ 221 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 222 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 223 FTIM0_NOR_TEADC(0x04) | \ 224 FTIM0_NOR_TEAHC(0x20)) 225 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 226 FTIM1_NOR_TRAD_NOR(0x1A) |\ 227 FTIM1_NOR_TSEQRAD_NOR(0x13)) 228 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 229 FTIM2_NOR_TCH(0x0E) | \ 230 FTIM2_NOR_TWPH(0x0E) | \ 231 FTIM2_NOR_TWP(0x1c)) 232 #define CONFIG_SYS_NOR_FTIM3 0x0 233 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 241 242 #define CONFIG_SYS_FLASH_EMPTY_INFO 243 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 244 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 245 246 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 247 #define CONFIG_FSL_QIXIS_V2 248 #define QIXIS_BASE 0xffdf0000 249 #ifdef CONFIG_PHYS_64BIT 250 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 251 #else 252 #define QIXIS_BASE_PHYS QIXIS_BASE 253 #endif 254 #define QIXIS_LBMAP_SWITCH 0x01 255 #define QIXIS_LBMAP_MASK 0x0f 256 #define QIXIS_LBMAP_SHIFT 0 257 #define QIXIS_LBMAP_DFLTBANK 0x00 258 #define QIXIS_LBMAP_ALTBANK 0x02 259 #define QIXIS_RST_CTL_RESET 0x31 260 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 261 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 262 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 263 264 #define CONFIG_SYS_CSPR3_EXT (0xf) 265 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 266 | CSPR_PORT_SIZE_8 \ 267 | CSPR_MSEL_GPCM \ 268 | CSPR_V) 269 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 270 #define CONFIG_SYS_CSOR3 0x0 271 /* QIXIS Timing parameters for IFC CS3 */ 272 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 273 FTIM0_GPCM_TEADC(0x0e) | \ 274 FTIM0_GPCM_TEAHC(0x0e)) 275 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 276 FTIM1_GPCM_TRAD(0x1f)) 277 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 278 FTIM2_GPCM_TCH(0x0) | \ 279 FTIM2_GPCM_TWP(0x1f)) 280 #define CONFIG_SYS_CS3_FTIM3 0x0 281 282 /* NAND Flash on IFC */ 283 #define CONFIG_NAND_FSL_IFC 284 #define CONFIG_SYS_NAND_BASE 0xff800000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 287 #else 288 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 289 #endif 290 291 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 292 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 293 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 294 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 295 | CSPR_V) 296 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 297 298 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 299 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 300 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 301 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 302 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 303 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 304 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 305 306 #define CONFIG_SYS_NAND_ONFI_DETECTION 307 308 /* ONFI NAND Flash mode0 Timing Params */ 309 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 310 FTIM0_NAND_TWP(0x18) | \ 311 FTIM0_NAND_TWCHT(0x07) | \ 312 FTIM0_NAND_TWH(0x0a)) 313 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 314 FTIM1_NAND_TWBE(0x39) | \ 315 FTIM1_NAND_TRR(0x0e) | \ 316 FTIM1_NAND_TRP(0x18)) 317 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 318 FTIM2_NAND_TREH(0x0a) | \ 319 FTIM2_NAND_TWHRE(0x1e)) 320 #define CONFIG_SYS_NAND_FTIM3 0x0 321 322 #define CONFIG_SYS_NAND_DDR_LAW 11 323 324 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 325 #define CONFIG_SYS_MAX_NAND_DEVICE 1 326 #define CONFIG_MTD_NAND_VERIFY_WRITE 327 #define CONFIG_CMD_NAND 328 329 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 330 331 #if defined(CONFIG_NAND) 332 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 333 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 334 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 335 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 336 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 337 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 338 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 339 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #else 349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 358 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 359 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 360 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 361 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 362 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 363 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 364 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 365 #endif 366 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 367 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 368 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 369 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 370 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 371 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 372 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 373 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 374 375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 376 377 #if defined(CONFIG_RAMBOOT_PBL) 378 #define CONFIG_SYS_RAMBOOT 379 #endif 380 381 #define CONFIG_BOARD_EARLY_INIT_R 382 #define CONFIG_MISC_INIT_R 383 384 #define CONFIG_HWCONFIG 385 386 /* define to use L1 as initial stack */ 387 #define CONFIG_L1_INIT_RAM 388 #define CONFIG_SYS_INIT_RAM_LOCK 389 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 390 #ifdef CONFIG_PHYS_64BIT 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 393 /* The assembler doesn't like typecast */ 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 395 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 396 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 397 #else 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 401 #endif 402 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 403 404 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 405 GENERATED_GBL_DATA_SIZE) 406 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 407 408 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 409 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 410 411 /* Serial Port - controlled on board with jumper J8 412 * open - index 2 413 * shorted - index 1 414 */ 415 #define CONFIG_CONS_INDEX 1 416 #define CONFIG_SYS_NS16550 417 #define CONFIG_SYS_NS16550_SERIAL 418 #define CONFIG_SYS_NS16550_REG_SIZE 1 419 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 420 421 #define CONFIG_SYS_BAUDRATE_TABLE \ 422 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 423 424 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 425 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 426 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 427 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 428 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 429 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 430 431 432 /* Use the HUSH parser */ 433 #define CONFIG_SYS_HUSH_PARSER 434 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 435 436 /* pass open firmware flat tree */ 437 #define CONFIG_OF_LIBFDT 438 #define CONFIG_OF_BOARD_SETUP 439 #define CONFIG_OF_STDOUT_VIA_ALIAS 440 441 /* new uImage format support */ 442 #define CONFIG_FIT 443 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 444 445 /* I2C */ 446 #define CONFIG_SYS_I2C 447 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 448 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 449 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 450 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 451 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 453 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 454 455 /* 456 * RTC configuration 457 */ 458 #define RTC 459 #define CONFIG_RTC_DS3231 1 460 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 461 462 /* 463 * RapidIO 464 */ 465 #ifdef CONFIG_SYS_SRIO 466 #ifdef CONFIG_SRIO1 467 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 470 #else 471 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 472 #endif 473 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 474 #endif 475 476 #ifdef CONFIG_SRIO2 477 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 480 #else 481 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 482 #endif 483 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 484 #endif 485 #endif 486 487 /* 488 * for slave u-boot IMAGE instored in master memory space, 489 * PHYS must be aligned based on the SIZE 490 */ 491 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 492 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 493 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 495 /* 496 * for slave UCODE and ENV instored in master memory space, 497 * PHYS must be aligned based on the SIZE 498 */ 499 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 500 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 501 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 502 503 /* slave core release by master*/ 504 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 505 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 506 507 /* 508 * SRIO_PCIE_BOOT - SLAVE 509 */ 510 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 511 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 512 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 513 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 514 #endif 515 516 /* 517 * eSPI - Enhanced SPI 518 */ 519 #define CONFIG_FSL_ESPI 520 #define CONFIG_SPI_FLASH 521 #define CONFIG_SPI_FLASH_SST 522 #define CONFIG_CMD_SF 523 #define CONFIG_SF_DEFAULT_SPEED 10000000 524 #define CONFIG_SF_DEFAULT_MODE 0 525 526 /* 527 * MAPLE 528 */ 529 #ifdef CONFIG_PHYS_64BIT 530 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 531 #else 532 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 533 #endif 534 535 /* 536 * General PCI 537 * Memory space is mapped 1-1, but I/O space must start from 0. 538 */ 539 540 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 541 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 542 #ifdef CONFIG_PHYS_64BIT 543 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 544 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 545 #else 546 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 547 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 548 #endif 549 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 550 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 551 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 554 #else 555 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 556 #endif 557 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 558 559 /* Qman/Bman */ 560 #ifndef CONFIG_NOBQFMAN 561 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 562 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 563 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 564 #ifdef CONFIG_PHYS_64BIT 565 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 566 #else 567 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 568 #endif 569 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 570 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 571 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 572 #ifdef CONFIG_PHYS_64BIT 573 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 574 #else 575 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 576 #endif 577 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 578 579 #define CONFIG_SYS_DPAA_FMAN 580 581 /* Default address of microcode for the Linux Fman driver */ 582 #if defined(CONFIG_SPIFLASH) 583 /* 584 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 585 * env, so we got 0x110000. 586 */ 587 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 588 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 589 #elif defined(CONFIG_SDCARD) 590 /* 591 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 592 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 593 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 594 */ 595 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 596 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 597 #elif defined(CONFIG_NAND) 598 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 599 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 600 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 601 /* 602 * Slave has no ucode locally, it can fetch this from remote. When implementing 603 * in two corenet boards, slave's ucode could be stored in master's memory 604 * space, the address can be mapped from slave TLB->slave LAW-> 605 * slave SRIO or PCIE outbound window->master inbound window-> 606 * master LAW->the ucode address in master's memory space. 607 */ 608 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 609 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 610 #else 611 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 612 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 613 #endif 614 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 615 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 616 #endif /* CONFIG_NOBQFMAN */ 617 618 #ifdef CONFIG_SYS_DPAA_FMAN 619 #define CONFIG_FMAN_ENET 620 #define CONFIG_PHYLIB_10G 621 #define CONFIG_PHY_VITESSE 622 #define CONFIG_PHY_TERANETICS 623 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 624 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 625 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 626 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 627 #endif 628 629 #ifdef CONFIG_PCI 630 #define CONFIG_PCI_INDIRECT_BRIDGE 631 #define CONFIG_NET_MULTI 632 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 633 #define CONFIG_E1000 634 635 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 636 #define CONFIG_DOS_PARTITION 637 #endif /* CONFIG_PCI */ 638 639 #ifdef CONFIG_FMAN_ENET 640 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 641 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 642 643 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 644 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 645 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 646 647 648 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 649 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 650 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 651 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 652 653 #define CONFIG_MII /* MII PHY management */ 654 #define CONFIG_ETHPRIME "FM1@DTSEC1" 655 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 656 #endif 657 658 /* 659 * Environment 660 */ 661 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 662 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 663 664 /* 665 * Command line configuration. 666 */ 667 #include <config_cmd_default.h> 668 669 #define CONFIG_CMD_DATE 670 #define CONFIG_CMD_DHCP 671 #define CONFIG_CMD_EEPROM 672 #define CONFIG_CMD_ELF 673 #define CONFIG_CMD_ERRATA 674 #define CONFIG_CMD_GREPENV 675 #define CONFIG_CMD_IRQ 676 #define CONFIG_CMD_I2C 677 #define CONFIG_CMD_MII 678 #define CONFIG_CMD_PING 679 #define CONFIG_CMD_REGINFO 680 #define CONFIG_CMD_SETEXPR 681 682 #ifdef CONFIG_PCI 683 #define CONFIG_CMD_PCI 684 #define CONFIG_CMD_NET 685 #endif 686 687 /* 688 * USB 689 */ 690 #define CONFIG_HAS_FSL_DR_USB 691 692 #ifdef CONFIG_HAS_FSL_DR_USB 693 #define CONFIG_USB_EHCI 694 695 #ifdef CONFIG_USB_EHCI 696 #define CONFIG_CMD_USB 697 #define CONFIG_USB_STORAGE 698 #define CONFIG_USB_EHCI_FSL 699 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 700 #define CONFIG_CMD_EXT2 701 #endif 702 #endif 703 704 /* 705 * Miscellaneous configurable options 706 */ 707 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 708 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 709 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 710 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 711 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 712 #ifdef CONFIG_CMD_KGDB 713 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 714 #else 715 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 716 #endif 717 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 718 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 719 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 720 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 721 722 /* 723 * For booting Linux, the board info and command line data 724 * have to be in the first 64 MB of memory, since this is 725 * the maximum mapped by the Linux kernel during initialization. 726 */ 727 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 728 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 729 730 #ifdef CONFIG_CMD_KGDB 731 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 732 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 733 #endif 734 735 /* 736 * Environment Configuration 737 */ 738 #define CONFIG_ROOTPATH "/opt/nfsroot" 739 #define CONFIG_BOOTFILE "uImage" 740 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 741 742 /* default location for tftp and bootm */ 743 #define CONFIG_LOADADDR 1000000 744 745 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 746 747 #define CONFIG_BAUDRATE 115200 748 749 #define __USB_PHY_TYPE ulpi 750 751 #define CONFIG_EXTRA_ENV_SETTINGS \ 752 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 753 "bank_intlv=cs0_cs1;" \ 754 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 755 "netdev=eth0\0" \ 756 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 757 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 758 "tftpflash=tftpboot $loadaddr $uboot && " \ 759 "protect off $ubootaddr +$filesize && " \ 760 "erase $ubootaddr +$filesize && " \ 761 "cp.b $loadaddr $ubootaddr $filesize && " \ 762 "protect on $ubootaddr +$filesize && " \ 763 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 764 "consoledev=ttyS0\0" \ 765 "ramdiskaddr=2000000\0" \ 766 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 767 "fdtaddr=c00000\0" \ 768 "fdtfile=b4860qds/b4860qds.dtb\0" \ 769 "bdev=sda3\0" \ 770 "c=ffe\0" 771 772 /* For emulation this causes u-boot to jump to the start of the proof point 773 app code automatically */ 774 #define CONFIG_PROOF_POINTS \ 775 "setenv bootargs root=/dev/$bdev rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "cpu 1 release 0x29000000 - - -;" \ 778 "cpu 2 release 0x29000000 - - -;" \ 779 "cpu 3 release 0x29000000 - - -;" \ 780 "cpu 4 release 0x29000000 - - -;" \ 781 "cpu 5 release 0x29000000 - - -;" \ 782 "cpu 6 release 0x29000000 - - -;" \ 783 "cpu 7 release 0x29000000 - - -;" \ 784 "go 0x29000000" 785 786 #define CONFIG_HVBOOT \ 787 "setenv bootargs config-addr=0x60000000; " \ 788 "bootm 0x01000000 - 0x00f00000" 789 790 #define CONFIG_ALU \ 791 "setenv bootargs root=/dev/$bdev rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "cpu 1 release 0x01000000 - - -;" \ 794 "cpu 2 release 0x01000000 - - -;" \ 795 "cpu 3 release 0x01000000 - - -;" \ 796 "cpu 4 release 0x01000000 - - -;" \ 797 "cpu 5 release 0x01000000 - - -;" \ 798 "cpu 6 release 0x01000000 - - -;" \ 799 "cpu 7 release 0x01000000 - - -;" \ 800 "go 0x01000000" 801 802 #define CONFIG_LINUX \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "setenv ramdiskaddr 0x02000000;" \ 806 "setenv fdtaddr 0x00c00000;" \ 807 "setenv loadaddr 0x1000000;" \ 808 "bootm $loadaddr $ramdiskaddr $fdtaddr" 809 810 #define CONFIG_HDBOOT \ 811 "setenv bootargs root=/dev/$bdev rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "tftp $loadaddr $bootfile;" \ 814 "tftp $fdtaddr $fdtfile;" \ 815 "bootm $loadaddr - $fdtaddr" 816 817 #define CONFIG_NFSBOOTCOMMAND \ 818 "setenv bootargs root=/dev/nfs rw " \ 819 "nfsroot=$serverip:$rootpath " \ 820 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 821 "console=$consoledev,$baudrate $othbootargs;" \ 822 "tftp $loadaddr $bootfile;" \ 823 "tftp $fdtaddr $fdtfile;" \ 824 "bootm $loadaddr - $fdtaddr" 825 826 #define CONFIG_RAMBOOTCOMMAND \ 827 "setenv bootargs root=/dev/ram rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "tftp $ramdiskaddr $ramdiskfile;" \ 830 "tftp $loadaddr $bootfile;" \ 831 "tftp $fdtaddr $fdtfile;" \ 832 "bootm $loadaddr $ramdiskaddr $fdtaddr" 833 834 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 835 836 #ifdef CONFIG_SECURE_BOOT 837 #include <asm/fsl_secure_boot.h> 838 #endif 839 840 #endif /* __CONFIG_H */ 841