1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #define CONFIG_B4860QDS 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 19 #ifndef CONFIG_NAND 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #else 23 #define CONFIG_SPL 24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 25 #define CONFIG_SPL_ENV_SUPPORT 26 #define CONFIG_SPL_SERIAL_SUPPORT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_LIBGENERIC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_I2C_SUPPORT 32 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_SYS_TEXT_BASE 0x00201000 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 #define CONFIG_SPL_NAND_SUPPORT 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 46 #define CONFIG_SPL_NAND_BOOT 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 #endif 54 #endif 55 56 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 57 /* Set 1M boot space */ 58 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 59 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 60 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 61 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 62 #define CONFIG_SYS_NO_FLASH 63 #endif 64 65 /* High Level Configuration Options */ 66 #define CONFIG_BOOKE 67 #define CONFIG_E500 /* BOOKE e500 family */ 68 #define CONFIG_E500MC /* BOOKE e500mc family */ 69 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 70 #define CONFIG_MP /* support multiple processors */ 71 72 #ifndef CONFIG_SYS_TEXT_BASE 73 #define CONFIG_SYS_TEXT_BASE 0xeff40000 74 #endif 75 76 #ifndef CONFIG_RESET_VECTOR_ADDRESS 77 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 78 #endif 79 80 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 81 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 82 #define CONFIG_FSL_IFC /* Enable IFC Support */ 83 #define CONFIG_PCI /* Enable PCI/PCIE */ 84 #define CONFIG_PCIE1 /* PCIE controler 1 */ 85 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 86 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 87 88 #ifndef CONFIG_PPC_B4420 89 #define CONFIG_SYS_SRIO 90 #define CONFIG_SRIO1 /* SRIO port 1 */ 91 #define CONFIG_SRIO2 /* SRIO port 2 */ 92 #define CONFIG_SRIO_PCIE_BOOT_MASTER 93 #endif 94 95 #define CONFIG_FSL_LAW /* Use common FSL init code */ 96 97 /* I2C bus multiplexer */ 98 #define I2C_MUX_PCA_ADDR 0x77 99 100 /* VSC Crossbar switches */ 101 #define CONFIG_VSC_CROSSBAR 102 #define I2C_CH_DEFAULT 0x8 103 #define I2C_CH_VSC3316 0xc 104 #define I2C_CH_VSC3308 0xd 105 106 #define VSC3316_TX_ADDRESS 0x70 107 #define VSC3316_RX_ADDRESS 0x71 108 #define VSC3308_TX_ADDRESS 0x02 109 #define VSC3308_RX_ADDRESS 0x03 110 111 /* IDT clock synthesizers */ 112 #define CONFIG_IDT8T49N222A 113 #define I2C_CH_IDT 0x9 114 115 #define IDT_SERDES1_ADDRESS 0x6E 116 #define IDT_SERDES2_ADDRESS 0x6C 117 118 #define CONFIG_ENV_OVERWRITE 119 120 #ifdef CONFIG_SYS_NO_FLASH 121 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 122 #define CONFIG_ENV_IS_NOWHERE 123 #endif 124 #else 125 #define CONFIG_FLASH_CFI_DRIVER 126 #define CONFIG_SYS_FLASH_CFI 127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 128 #endif 129 130 #if defined(CONFIG_SPIFLASH) 131 #define CONFIG_SYS_EXTRA_ENV_RELOC 132 #define CONFIG_ENV_IS_IN_SPI_FLASH 133 #define CONFIG_ENV_SPI_BUS 0 134 #define CONFIG_ENV_SPI_CS 0 135 #define CONFIG_ENV_SPI_MAX_HZ 10000000 136 #define CONFIG_ENV_SPI_MODE 0 137 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 138 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 139 #define CONFIG_ENV_SECT_SIZE 0x10000 140 #elif defined(CONFIG_SDCARD) 141 #define CONFIG_SYS_EXTRA_ENV_RELOC 142 #define CONFIG_ENV_IS_IN_MMC 143 #define CONFIG_SYS_MMC_ENV_DEV 0 144 #define CONFIG_ENV_SIZE 0x2000 145 #define CONFIG_ENV_OFFSET (512 * 1097) 146 #elif defined(CONFIG_NAND) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_IS_IN_NAND 149 #define CONFIG_ENV_SIZE 0x2000 150 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 151 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 152 #define CONFIG_ENV_IS_IN_REMOTE 153 #define CONFIG_ENV_ADDR 0xffe20000 154 #define CONFIG_ENV_SIZE 0x2000 155 #elif defined(CONFIG_ENV_IS_NOWHERE) 156 #define CONFIG_ENV_SIZE 0x2000 157 #else 158 #define CONFIG_ENV_IS_IN_FLASH 159 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 162 #endif 163 164 #ifndef __ASSEMBLY__ 165 unsigned long get_board_sys_clk(void); 166 unsigned long get_board_ddr_clk(void); 167 #endif 168 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 169 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 170 171 /* 172 * These can be toggled for performance analysis, otherwise use default. 173 */ 174 #define CONFIG_SYS_CACHE_STASHING 175 #define CONFIG_BTB /* toggle branch predition */ 176 #define CONFIG_DDR_ECC 177 #ifdef CONFIG_DDR_ECC 178 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 179 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 180 #endif 181 182 #define CONFIG_ENABLE_36BIT_PHYS 183 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_ADDR_MAP 186 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 187 #endif 188 189 #if 0 190 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 191 #endif 192 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 193 #define CONFIG_SYS_MEMTEST_END 0x00400000 194 #define CONFIG_SYS_ALT_MEMTEST 195 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 196 197 /* 198 * Config the L3 Cache as L3 SRAM 199 */ 200 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 201 #define CONFIG_SYS_L3_SIZE 256 << 10 202 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 203 #ifdef CONFIG_NAND 204 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 205 #endif 206 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 207 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 208 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 209 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 210 211 #ifdef CONFIG_PHYS_64BIT 212 #define CONFIG_SYS_DCSRBAR 0xf0000000 213 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 214 #endif 215 216 /* EEPROM */ 217 #define CONFIG_SYS_I2C_EEPROM_NXID 218 #define CONFIG_SYS_EEPROM_BUS_NUM 0 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 223 224 /* 225 * DDR Setup 226 */ 227 #define CONFIG_VERY_BIG_RAM 228 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 229 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 230 231 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 232 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 233 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 234 235 #define CONFIG_DDR_SPD 236 #define CONFIG_SYS_DDR_RAW_TIMING 237 #define CONFIG_SYS_FSL_DDR3 238 #ifndef CONFIG_SPL_BUILD 239 #define CONFIG_FSL_DDR_INTERACTIVE 240 #endif 241 242 #define CONFIG_SYS_SPD_BUS_NUM 0 243 #define SPD_EEPROM_ADDRESS1 0x51 244 #define SPD_EEPROM_ADDRESS2 0x53 245 246 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 247 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 248 249 /* 250 * IFC Definitions 251 */ 252 #define CONFIG_SYS_FLASH_BASE 0xe0000000 253 #ifdef CONFIG_PHYS_64BIT 254 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 255 #else 256 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 257 #endif 258 259 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 261 + 0x8000000) | \ 262 CSPR_PORT_SIZE_16 | \ 263 CSPR_MSEL_NOR | \ 264 CSPR_V) 265 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 266 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 267 CSPR_PORT_SIZE_16 | \ 268 CSPR_MSEL_NOR | \ 269 CSPR_V) 270 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 271 /* NOR Flash Timing Params */ 272 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 273 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 274 FTIM0_NOR_TEADC(0x04) | \ 275 FTIM0_NOR_TEAHC(0x20)) 276 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 277 FTIM1_NOR_TRAD_NOR(0x1A) |\ 278 FTIM1_NOR_TSEQRAD_NOR(0x13)) 279 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 280 FTIM2_NOR_TCH(0x0E) | \ 281 FTIM2_NOR_TWPH(0x0E) | \ 282 FTIM2_NOR_TWP(0x1c)) 283 #define CONFIG_SYS_NOR_FTIM3 0x0 284 285 #define CONFIG_SYS_FLASH_QUIET_TEST 286 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 287 288 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 289 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 290 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 291 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 292 293 #define CONFIG_SYS_FLASH_EMPTY_INFO 294 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 295 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 296 297 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 298 #define CONFIG_FSL_QIXIS_V2 299 #define QIXIS_BASE 0xffdf0000 300 #ifdef CONFIG_PHYS_64BIT 301 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 302 #else 303 #define QIXIS_BASE_PHYS QIXIS_BASE 304 #endif 305 #define QIXIS_LBMAP_SWITCH 0x01 306 #define QIXIS_LBMAP_MASK 0x0f 307 #define QIXIS_LBMAP_SHIFT 0 308 #define QIXIS_LBMAP_DFLTBANK 0x00 309 #define QIXIS_LBMAP_ALTBANK 0x02 310 #define QIXIS_RST_CTL_RESET 0x31 311 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 312 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 313 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 314 315 #define CONFIG_SYS_CSPR3_EXT (0xf) 316 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 317 | CSPR_PORT_SIZE_8 \ 318 | CSPR_MSEL_GPCM \ 319 | CSPR_V) 320 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 321 #define CONFIG_SYS_CSOR3 0x0 322 /* QIXIS Timing parameters for IFC CS3 */ 323 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 324 FTIM0_GPCM_TEADC(0x0e) | \ 325 FTIM0_GPCM_TEAHC(0x0e)) 326 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 327 FTIM1_GPCM_TRAD(0x1f)) 328 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 329 FTIM2_GPCM_TCH(0x0) | \ 330 FTIM2_GPCM_TWP(0x1f)) 331 #define CONFIG_SYS_CS3_FTIM3 0x0 332 333 /* NAND Flash on IFC */ 334 #define CONFIG_NAND_FSL_IFC 335 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 336 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 337 #define CONFIG_SYS_NAND_BASE 0xff800000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 340 #else 341 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 342 #endif 343 344 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 345 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 346 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 347 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 348 | CSPR_V) 349 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 350 351 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 352 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 353 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 354 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 355 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 356 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 357 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 358 359 #define CONFIG_SYS_NAND_ONFI_DETECTION 360 361 /* ONFI NAND Flash mode0 Timing Params */ 362 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 363 FTIM0_NAND_TWP(0x18) | \ 364 FTIM0_NAND_TWCHT(0x07) | \ 365 FTIM0_NAND_TWH(0x0a)) 366 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 367 FTIM1_NAND_TWBE(0x39) | \ 368 FTIM1_NAND_TRR(0x0e) | \ 369 FTIM1_NAND_TRP(0x18)) 370 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 371 FTIM2_NAND_TREH(0x0a) | \ 372 FTIM2_NAND_TWHRE(0x1e)) 373 #define CONFIG_SYS_NAND_FTIM3 0x0 374 375 #define CONFIG_SYS_NAND_DDR_LAW 11 376 377 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 378 #define CONFIG_SYS_MAX_NAND_DEVICE 1 379 #define CONFIG_MTD_NAND_VERIFY_WRITE 380 #define CONFIG_CMD_NAND 381 382 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 383 384 #if defined(CONFIG_NAND) 385 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 386 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 387 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 388 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 389 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 390 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 391 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 392 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 393 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 394 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 395 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 396 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 397 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 398 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 399 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 400 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 401 #else 402 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 403 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 404 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 405 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 406 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 407 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 408 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 409 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 410 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 411 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 412 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 413 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 414 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 415 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 416 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 417 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 418 #endif 419 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 420 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 421 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 422 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 423 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 424 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 425 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 426 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 427 428 #ifdef CONFIG_SPL_BUILD 429 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 430 #else 431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 432 #endif 433 434 #if defined(CONFIG_RAMBOOT_PBL) 435 #define CONFIG_SYS_RAMBOOT 436 #endif 437 438 #define CONFIG_BOARD_EARLY_INIT_R 439 #define CONFIG_MISC_INIT_R 440 441 #define CONFIG_HWCONFIG 442 443 /* define to use L1 as initial stack */ 444 #define CONFIG_L1_INIT_RAM 445 #define CONFIG_SYS_INIT_RAM_LOCK 446 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 450 /* The assembler doesn't like typecast */ 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 452 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 453 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 454 #else 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 458 #endif 459 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 460 461 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 462 GENERATED_GBL_DATA_SIZE) 463 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 464 465 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 466 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 467 468 /* Serial Port - controlled on board with jumper J8 469 * open - index 2 470 * shorted - index 1 471 */ 472 #define CONFIG_CONS_INDEX 1 473 #define CONFIG_SYS_NS16550 474 #define CONFIG_SYS_NS16550_SERIAL 475 #define CONFIG_SYS_NS16550_REG_SIZE 1 476 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 477 478 #define CONFIG_SYS_BAUDRATE_TABLE \ 479 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 480 481 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 482 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 483 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 484 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 485 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 486 #ifndef CONFIG_SPL_BUILD 487 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 488 #endif 489 490 491 /* Use the HUSH parser */ 492 #define CONFIG_SYS_HUSH_PARSER 493 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 494 495 /* pass open firmware flat tree */ 496 #define CONFIG_OF_LIBFDT 497 #define CONFIG_OF_BOARD_SETUP 498 #define CONFIG_OF_STDOUT_VIA_ALIAS 499 500 /* new uImage format support */ 501 #define CONFIG_FIT 502 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 503 504 /* I2C */ 505 #define CONFIG_SYS_I2C 506 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 507 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 508 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 509 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 510 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 511 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 512 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 513 514 /* 515 * RTC configuration 516 */ 517 #define RTC 518 #define CONFIG_RTC_DS3231 1 519 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 520 521 /* 522 * RapidIO 523 */ 524 #ifdef CONFIG_SYS_SRIO 525 #ifdef CONFIG_SRIO1 526 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 527 #ifdef CONFIG_PHYS_64BIT 528 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 529 #else 530 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 531 #endif 532 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 533 #endif 534 535 #ifdef CONFIG_SRIO2 536 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 537 #ifdef CONFIG_PHYS_64BIT 538 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 539 #else 540 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 541 #endif 542 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 543 #endif 544 #endif 545 546 /* 547 * for slave u-boot IMAGE instored in master memory space, 548 * PHYS must be aligned based on the SIZE 549 */ 550 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 551 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 552 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 553 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 554 /* 555 * for slave UCODE and ENV instored in master memory space, 556 * PHYS must be aligned based on the SIZE 557 */ 558 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 559 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 560 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 561 562 /* slave core release by master*/ 563 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 564 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 565 566 /* 567 * SRIO_PCIE_BOOT - SLAVE 568 */ 569 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 570 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 571 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 572 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 573 #endif 574 575 /* 576 * eSPI - Enhanced SPI 577 */ 578 #define CONFIG_FSL_ESPI 579 #define CONFIG_SPI_FLASH 580 #define CONFIG_SPI_FLASH_SST 581 #define CONFIG_CMD_SF 582 #define CONFIG_SF_DEFAULT_SPEED 10000000 583 #define CONFIG_SF_DEFAULT_MODE 0 584 585 /* 586 * MAPLE 587 */ 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 590 #else 591 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 592 #endif 593 594 /* 595 * General PCI 596 * Memory space is mapped 1-1, but I/O space must start from 0. 597 */ 598 599 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 600 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 604 #else 605 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 606 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 607 #endif 608 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 609 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 610 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 611 #ifdef CONFIG_PHYS_64BIT 612 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 613 #else 614 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 615 #endif 616 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 617 618 /* Qman/Bman */ 619 #ifndef CONFIG_NOBQFMAN 620 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 621 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 622 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 623 #ifdef CONFIG_PHYS_64BIT 624 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 625 #else 626 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 627 #endif 628 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 629 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 630 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 631 #ifdef CONFIG_PHYS_64BIT 632 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 633 #else 634 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 635 #endif 636 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 637 638 #define CONFIG_SYS_DPAA_FMAN 639 640 #define CONFIG_SYS_DPAA_RMAN 641 642 /* Default address of microcode for the Linux Fman driver */ 643 #if defined(CONFIG_SPIFLASH) 644 /* 645 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 646 * env, so we got 0x110000. 647 */ 648 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 649 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 650 #elif defined(CONFIG_SDCARD) 651 /* 652 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 653 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 654 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 655 */ 656 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 657 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 658 #elif defined(CONFIG_NAND) 659 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 660 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 661 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 662 /* 663 * Slave has no ucode locally, it can fetch this from remote. When implementing 664 * in two corenet boards, slave's ucode could be stored in master's memory 665 * space, the address can be mapped from slave TLB->slave LAW-> 666 * slave SRIO or PCIE outbound window->master inbound window-> 667 * master LAW->the ucode address in master's memory space. 668 */ 669 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 670 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 671 #else 672 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 673 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 674 #endif 675 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 676 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 677 #endif /* CONFIG_NOBQFMAN */ 678 679 #ifdef CONFIG_SYS_DPAA_FMAN 680 #define CONFIG_FMAN_ENET 681 #define CONFIG_PHYLIB_10G 682 #define CONFIG_PHY_VITESSE 683 #define CONFIG_PHY_TERANETICS 684 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 685 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 686 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 687 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 688 #endif 689 690 #ifdef CONFIG_PCI 691 #define CONFIG_PCI_INDIRECT_BRIDGE 692 #define CONFIG_NET_MULTI 693 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 694 #define CONFIG_E1000 695 696 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 697 #define CONFIG_DOS_PARTITION 698 #endif /* CONFIG_PCI */ 699 700 #ifdef CONFIG_FMAN_ENET 701 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 702 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 703 704 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 705 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 706 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 707 708 709 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 710 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 711 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 712 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 713 714 #define CONFIG_MII /* MII PHY management */ 715 #define CONFIG_ETHPRIME "FM1@DTSEC1" 716 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 717 #endif 718 719 /* 720 * Environment 721 */ 722 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 723 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 724 725 /* 726 * Command line configuration. 727 */ 728 #include <config_cmd_default.h> 729 730 #define CONFIG_CMD_DATE 731 #define CONFIG_CMD_DHCP 732 #define CONFIG_CMD_EEPROM 733 #define CONFIG_CMD_ELF 734 #define CONFIG_CMD_ERRATA 735 #define CONFIG_CMD_GREPENV 736 #define CONFIG_CMD_IRQ 737 #define CONFIG_CMD_I2C 738 #define CONFIG_CMD_MII 739 #define CONFIG_CMD_PING 740 #define CONFIG_CMD_REGINFO 741 #define CONFIG_CMD_SETEXPR 742 743 #ifdef CONFIG_PCI 744 #define CONFIG_CMD_PCI 745 #define CONFIG_CMD_NET 746 #endif 747 748 /* 749 * USB 750 */ 751 #define CONFIG_HAS_FSL_DR_USB 752 753 #ifdef CONFIG_HAS_FSL_DR_USB 754 #define CONFIG_USB_EHCI 755 756 #ifdef CONFIG_USB_EHCI 757 #define CONFIG_CMD_USB 758 #define CONFIG_USB_STORAGE 759 #define CONFIG_USB_EHCI_FSL 760 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 761 #define CONFIG_CMD_EXT2 762 #endif 763 #endif 764 765 /* 766 * Miscellaneous configurable options 767 */ 768 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 769 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 770 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 771 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 772 #ifdef CONFIG_CMD_KGDB 773 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 774 #else 775 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 776 #endif 777 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 778 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 779 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 780 781 /* 782 * For booting Linux, the board info and command line data 783 * have to be in the first 64 MB of memory, since this is 784 * the maximum mapped by the Linux kernel during initialization. 785 */ 786 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 787 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 788 789 #ifdef CONFIG_CMD_KGDB 790 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 791 #endif 792 793 /* 794 * Environment Configuration 795 */ 796 #define CONFIG_ROOTPATH "/opt/nfsroot" 797 #define CONFIG_BOOTFILE "uImage" 798 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 799 800 /* default location for tftp and bootm */ 801 #define CONFIG_LOADADDR 1000000 802 803 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 804 805 #define CONFIG_BAUDRATE 115200 806 807 #define __USB_PHY_TYPE ulpi 808 809 #define CONFIG_EXTRA_ENV_SETTINGS \ 810 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 811 "bank_intlv=cs0_cs1;" \ 812 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 813 "netdev=eth0\0" \ 814 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 815 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 816 "tftpflash=tftpboot $loadaddr $uboot && " \ 817 "protect off $ubootaddr +$filesize && " \ 818 "erase $ubootaddr +$filesize && " \ 819 "cp.b $loadaddr $ubootaddr $filesize && " \ 820 "protect on $ubootaddr +$filesize && " \ 821 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 822 "consoledev=ttyS0\0" \ 823 "ramdiskaddr=2000000\0" \ 824 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 825 "fdtaddr=c00000\0" \ 826 "fdtfile=b4860qds/b4860qds.dtb\0" \ 827 "bdev=sda3\0" \ 828 "c=ffe\0" 829 830 /* For emulation this causes u-boot to jump to the start of the proof point 831 app code automatically */ 832 #define CONFIG_PROOF_POINTS \ 833 "setenv bootargs root=/dev/$bdev rw " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "cpu 1 release 0x29000000 - - -;" \ 836 "cpu 2 release 0x29000000 - - -;" \ 837 "cpu 3 release 0x29000000 - - -;" \ 838 "cpu 4 release 0x29000000 - - -;" \ 839 "cpu 5 release 0x29000000 - - -;" \ 840 "cpu 6 release 0x29000000 - - -;" \ 841 "cpu 7 release 0x29000000 - - -;" \ 842 "go 0x29000000" 843 844 #define CONFIG_HVBOOT \ 845 "setenv bootargs config-addr=0x60000000; " \ 846 "bootm 0x01000000 - 0x00f00000" 847 848 #define CONFIG_ALU \ 849 "setenv bootargs root=/dev/$bdev rw " \ 850 "console=$consoledev,$baudrate $othbootargs;" \ 851 "cpu 1 release 0x01000000 - - -;" \ 852 "cpu 2 release 0x01000000 - - -;" \ 853 "cpu 3 release 0x01000000 - - -;" \ 854 "cpu 4 release 0x01000000 - - -;" \ 855 "cpu 5 release 0x01000000 - - -;" \ 856 "cpu 6 release 0x01000000 - - -;" \ 857 "cpu 7 release 0x01000000 - - -;" \ 858 "go 0x01000000" 859 860 #define CONFIG_LINUX \ 861 "setenv bootargs root=/dev/ram rw " \ 862 "console=$consoledev,$baudrate $othbootargs;" \ 863 "setenv ramdiskaddr 0x02000000;" \ 864 "setenv fdtaddr 0x00c00000;" \ 865 "setenv loadaddr 0x1000000;" \ 866 "bootm $loadaddr $ramdiskaddr $fdtaddr" 867 868 #define CONFIG_HDBOOT \ 869 "setenv bootargs root=/dev/$bdev rw " \ 870 "console=$consoledev,$baudrate $othbootargs;" \ 871 "tftp $loadaddr $bootfile;" \ 872 "tftp $fdtaddr $fdtfile;" \ 873 "bootm $loadaddr - $fdtaddr" 874 875 #define CONFIG_NFSBOOTCOMMAND \ 876 "setenv bootargs root=/dev/nfs rw " \ 877 "nfsroot=$serverip:$rootpath " \ 878 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 879 "console=$consoledev,$baudrate $othbootargs;" \ 880 "tftp $loadaddr $bootfile;" \ 881 "tftp $fdtaddr $fdtfile;" \ 882 "bootm $loadaddr - $fdtaddr" 883 884 #define CONFIG_RAMBOOTCOMMAND \ 885 "setenv bootargs root=/dev/ram rw " \ 886 "console=$consoledev,$baudrate $othbootargs;" \ 887 "tftp $ramdiskaddr $ramdiskfile;" \ 888 "tftp $loadaddr $bootfile;" \ 889 "tftp $fdtaddr $fdtfile;" \ 890 "bootm $loadaddr $ramdiskaddr $fdtaddr" 891 892 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 893 894 #include <asm/fsl_secure_boot.h> 895 896 #endif /* __CONFIG_H */ 897