1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SYS_TEXT_BASE 0x00201000 23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 24 #define CONFIG_SPL_PAD_TO 0x40000 25 #define CONFIG_SPL_MAX_SIZE 0x28000 26 #define RESET_VECTOR_OFFSET 0x27FFC 27 #define BOOT_PAGE_OFFSET 0x27000 28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 33 #define CONFIG_SPL_NAND_BOOT 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #endif 39 #endif 40 #endif 41 42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 43 /* Set 1M boot space */ 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 46 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 48 #endif 49 50 /* High Level Configuration Options */ 51 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 52 #define CONFIG_MP /* support multiple processors */ 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xeff40000 56 #endif 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #ifndef CONFIG_ARCH_B4420 69 #define CONFIG_SYS_SRIO 70 #define CONFIG_SRIO1 /* SRIO port 1 */ 71 #define CONFIG_SRIO2 /* SRIO port 2 */ 72 #define CONFIG_SRIO_PCIE_BOOT_MASTER 73 #endif 74 75 /* I2C bus multiplexer */ 76 #define I2C_MUX_PCA_ADDR 0x77 77 78 /* VSC Crossbar switches */ 79 #define CONFIG_VSC_CROSSBAR 80 #define I2C_CH_DEFAULT 0x8 81 #define I2C_CH_VSC3316 0xc 82 #define I2C_CH_VSC3308 0xd 83 84 #define VSC3316_TX_ADDRESS 0x70 85 #define VSC3316_RX_ADDRESS 0x71 86 #define VSC3308_TX_ADDRESS 0x02 87 #define VSC3308_RX_ADDRESS 0x03 88 89 /* IDT clock synthesizers */ 90 #define CONFIG_IDT8T49N222A 91 #define I2C_CH_IDT 0x9 92 93 #define IDT_SERDES1_ADDRESS 0x6E 94 #define IDT_SERDES2_ADDRESS 0x6C 95 96 /* Voltage monitor on channel 2*/ 97 #define I2C_MUX_CH_VOL_MONITOR 0xa 98 #define I2C_VOL_MONITOR_ADDR 0x40 99 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 100 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 101 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 102 103 #define CONFIG_ZM7300 104 #define I2C_MUX_CH_DPM 0xa 105 #define I2C_DPM_ADDR 0x28 106 107 #define CONFIG_ENV_OVERWRITE 108 109 #ifndef CONFIG_MTD_NOR_FLASH 110 #else 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 114 #endif 115 116 #if defined(CONFIG_SPIFLASH) 117 #define CONFIG_SYS_EXTRA_ENV_RELOC 118 #define CONFIG_ENV_SPI_BUS 0 119 #define CONFIG_ENV_SPI_CS 0 120 #define CONFIG_ENV_SPI_MAX_HZ 10000000 121 #define CONFIG_ENV_SPI_MODE 0 122 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 123 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 124 #define CONFIG_ENV_SECT_SIZE 0x10000 125 #elif defined(CONFIG_SDCARD) 126 #define CONFIG_SYS_EXTRA_ENV_RELOC 127 #define CONFIG_SYS_MMC_ENV_DEV 0 128 #define CONFIG_ENV_SIZE 0x2000 129 #define CONFIG_ENV_OFFSET (512 * 1097) 130 #elif defined(CONFIG_NAND) 131 #define CONFIG_SYS_EXTRA_ENV_RELOC 132 #define CONFIG_ENV_SIZE 0x2000 133 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 134 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 135 #define CONFIG_ENV_ADDR 0xffe20000 136 #define CONFIG_ENV_SIZE 0x2000 137 #elif defined(CONFIG_ENV_IS_NOWHERE) 138 #define CONFIG_ENV_SIZE 0x2000 139 #else 140 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 141 #define CONFIG_ENV_SIZE 0x2000 142 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 143 #endif 144 145 #ifndef __ASSEMBLY__ 146 unsigned long get_board_sys_clk(void); 147 unsigned long get_board_ddr_clk(void); 148 #endif 149 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 150 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 151 152 /* 153 * These can be toggled for performance analysis, otherwise use default. 154 */ 155 #define CONFIG_SYS_CACHE_STASHING 156 #define CONFIG_BTB /* toggle branch predition */ 157 #define CONFIG_DDR_ECC 158 #ifdef CONFIG_DDR_ECC 159 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 160 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 161 #endif 162 163 #define CONFIG_ENABLE_36BIT_PHYS 164 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_ADDR_MAP 167 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 168 #endif 169 170 #if 0 171 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 172 #endif 173 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 174 #define CONFIG_SYS_MEMTEST_END 0x00400000 175 #define CONFIG_SYS_ALT_MEMTEST 176 177 /* 178 * Config the L3 Cache as L3 SRAM 179 */ 180 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 181 #define CONFIG_SYS_L3_SIZE 256 << 10 182 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 183 #ifdef CONFIG_NAND 184 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 185 #endif 186 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 187 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 188 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 189 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 190 191 #ifdef CONFIG_PHYS_64BIT 192 #define CONFIG_SYS_DCSRBAR 0xf0000000 193 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 194 #endif 195 196 /* EEPROM */ 197 #define CONFIG_ID_EEPROM 198 #define CONFIG_SYS_I2C_EEPROM_NXID 199 #define CONFIG_SYS_EEPROM_BUS_NUM 0 200 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 201 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 203 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 204 205 /* 206 * DDR Setup 207 */ 208 #define CONFIG_VERY_BIG_RAM 209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 210 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 211 212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 213 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 214 215 #define CONFIG_DDR_SPD 216 #define CONFIG_SYS_DDR_RAW_TIMING 217 #ifndef CONFIG_SPL_BUILD 218 #define CONFIG_FSL_DDR_INTERACTIVE 219 #endif 220 221 #define CONFIG_SYS_SPD_BUS_NUM 0 222 #define SPD_EEPROM_ADDRESS1 0x51 223 #define SPD_EEPROM_ADDRESS2 0x53 224 225 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 226 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 227 228 /* 229 * IFC Definitions 230 */ 231 #define CONFIG_SYS_FLASH_BASE 0xe0000000 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 234 #else 235 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 236 #endif 237 238 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 240 + 0x8000000) | \ 241 CSPR_PORT_SIZE_16 | \ 242 CSPR_MSEL_NOR | \ 243 CSPR_V) 244 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 245 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 246 CSPR_PORT_SIZE_16 | \ 247 CSPR_MSEL_NOR | \ 248 CSPR_V) 249 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 250 /* NOR Flash Timing Params */ 251 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 252 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 253 FTIM0_NOR_TEADC(0x04) | \ 254 FTIM0_NOR_TEAHC(0x20)) 255 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 256 FTIM1_NOR_TRAD_NOR(0x1A) |\ 257 FTIM1_NOR_TSEQRAD_NOR(0x13)) 258 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 259 FTIM2_NOR_TCH(0x0E) | \ 260 FTIM2_NOR_TWPH(0x0E) | \ 261 FTIM2_NOR_TWP(0x1c)) 262 #define CONFIG_SYS_NOR_FTIM3 0x0 263 264 #define CONFIG_SYS_FLASH_QUIET_TEST 265 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 266 267 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 268 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 269 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 270 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 271 272 #define CONFIG_SYS_FLASH_EMPTY_INFO 273 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 274 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 275 276 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 277 #define CONFIG_FSL_QIXIS_V2 278 #define QIXIS_BASE 0xffdf0000 279 #ifdef CONFIG_PHYS_64BIT 280 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 281 #else 282 #define QIXIS_BASE_PHYS QIXIS_BASE 283 #endif 284 #define QIXIS_LBMAP_SWITCH 0x01 285 #define QIXIS_LBMAP_MASK 0x0f 286 #define QIXIS_LBMAP_SHIFT 0 287 #define QIXIS_LBMAP_DFLTBANK 0x00 288 #define QIXIS_LBMAP_ALTBANK 0x02 289 #define QIXIS_RST_CTL_RESET 0x31 290 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 291 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 292 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 293 294 #define CONFIG_SYS_CSPR3_EXT (0xf) 295 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 296 | CSPR_PORT_SIZE_8 \ 297 | CSPR_MSEL_GPCM \ 298 | CSPR_V) 299 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 300 #define CONFIG_SYS_CSOR3 0x0 301 /* QIXIS Timing parameters for IFC CS3 */ 302 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 303 FTIM0_GPCM_TEADC(0x0e) | \ 304 FTIM0_GPCM_TEAHC(0x0e)) 305 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 306 FTIM1_GPCM_TRAD(0x1f)) 307 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 308 FTIM2_GPCM_TCH(0x8) | \ 309 FTIM2_GPCM_TWP(0x1f)) 310 #define CONFIG_SYS_CS3_FTIM3 0x0 311 312 /* NAND Flash on IFC */ 313 #define CONFIG_NAND_FSL_IFC 314 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 315 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 316 #define CONFIG_SYS_NAND_BASE 0xff800000 317 #ifdef CONFIG_PHYS_64BIT 318 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 319 #else 320 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 321 #endif 322 323 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 324 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 325 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 326 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 327 | CSPR_V) 328 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 329 330 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 331 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 332 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 333 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 334 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 335 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 336 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 337 338 #define CONFIG_SYS_NAND_ONFI_DETECTION 339 340 /* ONFI NAND Flash mode0 Timing Params */ 341 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 342 FTIM0_NAND_TWP(0x18) | \ 343 FTIM0_NAND_TWCHT(0x07) | \ 344 FTIM0_NAND_TWH(0x0a)) 345 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 346 FTIM1_NAND_TWBE(0x39) | \ 347 FTIM1_NAND_TRR(0x0e) | \ 348 FTIM1_NAND_TRP(0x18)) 349 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 350 FTIM2_NAND_TREH(0x0a) | \ 351 FTIM2_NAND_TWHRE(0x1e)) 352 #define CONFIG_SYS_NAND_FTIM3 0x0 353 354 #define CONFIG_SYS_NAND_DDR_LAW 11 355 356 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 357 #define CONFIG_SYS_MAX_NAND_DEVICE 1 358 359 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 360 361 #if defined(CONFIG_NAND) 362 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 363 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 364 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 365 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 366 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 367 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 368 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 369 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 370 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 371 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 372 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #else 379 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 380 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 381 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 382 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 383 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 384 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 385 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 386 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 387 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 388 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 389 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 390 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 391 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 392 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 393 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 394 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 395 #endif 396 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 397 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 398 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 399 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 400 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 401 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 402 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 403 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 404 405 #ifdef CONFIG_SPL_BUILD 406 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 407 #else 408 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 409 #endif 410 411 #if defined(CONFIG_RAMBOOT_PBL) 412 #define CONFIG_SYS_RAMBOOT 413 #endif 414 415 #define CONFIG_BOARD_EARLY_INIT_R 416 #define CONFIG_MISC_INIT_R 417 418 #define CONFIG_HWCONFIG 419 420 /* define to use L1 as initial stack */ 421 #define CONFIG_L1_INIT_RAM 422 #define CONFIG_SYS_INIT_RAM_LOCK 423 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 427 /* The assembler doesn't like typecast */ 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 429 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 430 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 431 #else 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 435 #endif 436 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 437 438 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 439 GENERATED_GBL_DATA_SIZE) 440 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 441 442 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 443 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 444 445 /* Serial Port - controlled on board with jumper J8 446 * open - index 2 447 * shorted - index 1 448 */ 449 #define CONFIG_CONS_INDEX 1 450 #define CONFIG_SYS_NS16550_SERIAL 451 #define CONFIG_SYS_NS16550_REG_SIZE 1 452 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 453 454 #define CONFIG_SYS_BAUDRATE_TABLE \ 455 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 456 457 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 458 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 459 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 460 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 461 462 /* I2C */ 463 #define CONFIG_SYS_I2C 464 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 465 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 466 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 467 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 468 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 469 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 470 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 471 472 /* 473 * RTC configuration 474 */ 475 #define RTC 476 #define CONFIG_RTC_DS3231 1 477 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 478 479 /* 480 * RapidIO 481 */ 482 #ifdef CONFIG_SYS_SRIO 483 #ifdef CONFIG_SRIO1 484 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 487 #else 488 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 489 #endif 490 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 491 #endif 492 493 #ifdef CONFIG_SRIO2 494 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 495 #ifdef CONFIG_PHYS_64BIT 496 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 497 #else 498 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 499 #endif 500 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 501 #endif 502 #endif 503 504 /* 505 * for slave u-boot IMAGE instored in master memory space, 506 * PHYS must be aligned based on the SIZE 507 */ 508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 512 /* 513 * for slave UCODE and ENV instored in master memory space, 514 * PHYS must be aligned based on the SIZE 515 */ 516 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 519 520 /* slave core release by master*/ 521 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 522 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 523 524 /* 525 * SRIO_PCIE_BOOT - SLAVE 526 */ 527 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 528 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 529 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 530 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 531 #endif 532 533 /* 534 * eSPI - Enhanced SPI 535 */ 536 #define CONFIG_SF_DEFAULT_SPEED 10000000 537 #define CONFIG_SF_DEFAULT_MODE 0 538 539 /* 540 * MAPLE 541 */ 542 #ifdef CONFIG_PHYS_64BIT 543 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 544 #else 545 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 546 #endif 547 548 /* 549 * General PCI 550 * Memory space is mapped 1-1, but I/O space must start from 0. 551 */ 552 553 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 554 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 555 #ifdef CONFIG_PHYS_64BIT 556 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 558 #else 559 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 560 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 561 #endif 562 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 563 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 564 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 565 #ifdef CONFIG_PHYS_64BIT 566 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 567 #else 568 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 569 #endif 570 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 571 572 /* Qman/Bman */ 573 #ifndef CONFIG_NOBQFMAN 574 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 575 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 576 #ifdef CONFIG_PHYS_64BIT 577 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 578 #else 579 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 580 #endif 581 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 582 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 583 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 584 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 585 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 586 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 587 CONFIG_SYS_BMAN_CENA_SIZE) 588 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 589 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 590 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 591 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 592 #ifdef CONFIG_PHYS_64BIT 593 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 594 #else 595 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 596 #endif 597 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 598 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 599 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 600 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 601 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 602 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 603 CONFIG_SYS_QMAN_CENA_SIZE) 604 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 605 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 606 607 #define CONFIG_SYS_DPAA_FMAN 608 609 #define CONFIG_SYS_DPAA_RMAN 610 611 /* Default address of microcode for the Linux Fman driver */ 612 #if defined(CONFIG_SPIFLASH) 613 /* 614 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 615 * env, so we got 0x110000. 616 */ 617 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 618 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 619 #elif defined(CONFIG_SDCARD) 620 /* 621 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 622 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 623 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 624 */ 625 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 626 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 627 #elif defined(CONFIG_NAND) 628 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 629 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 630 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 631 /* 632 * Slave has no ucode locally, it can fetch this from remote. When implementing 633 * in two corenet boards, slave's ucode could be stored in master's memory 634 * space, the address can be mapped from slave TLB->slave LAW-> 635 * slave SRIO or PCIE outbound window->master inbound window-> 636 * master LAW->the ucode address in master's memory space. 637 */ 638 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 639 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 640 #else 641 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 642 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 643 #endif 644 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 645 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 646 #endif /* CONFIG_NOBQFMAN */ 647 648 #ifdef CONFIG_SYS_DPAA_FMAN 649 #define CONFIG_FMAN_ENET 650 #define CONFIG_PHYLIB_10G 651 #define CONFIG_PHY_VITESSE 652 #define CONFIG_PHY_TERANETICS 653 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 654 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 655 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 656 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 657 #endif 658 659 #ifdef CONFIG_PCI 660 #define CONFIG_PCI_INDIRECT_BRIDGE 661 662 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 663 #endif /* CONFIG_PCI */ 664 665 #ifdef CONFIG_FMAN_ENET 666 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 667 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 668 669 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 670 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 671 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 672 673 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 674 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 675 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 676 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 677 678 #define CONFIG_MII /* MII PHY management */ 679 #define CONFIG_ETHPRIME "FM1@DTSEC1" 680 #endif 681 682 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 683 684 /* 685 * Environment 686 */ 687 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 688 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 689 690 /* 691 * USB 692 */ 693 #define CONFIG_HAS_FSL_DR_USB 694 695 #ifdef CONFIG_HAS_FSL_DR_USB 696 #ifdef CONFIG_USB_EHCI_HCD 697 #define CONFIG_USB_EHCI_FSL 698 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 699 #endif 700 #endif 701 702 /* 703 * Miscellaneous configurable options 704 */ 705 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 706 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 707 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 708 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 709 710 /* 711 * For booting Linux, the board info and command line data 712 * have to be in the first 64 MB of memory, since this is 713 * the maximum mapped by the Linux kernel during initialization. 714 */ 715 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 716 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 717 718 #ifdef CONFIG_CMD_KGDB 719 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 720 #endif 721 722 /* 723 * Environment Configuration 724 */ 725 #define CONFIG_ROOTPATH "/opt/nfsroot" 726 #define CONFIG_BOOTFILE "uImage" 727 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 728 729 /* default location for tftp and bootm */ 730 #define CONFIG_LOADADDR 1000000 731 732 #define __USB_PHY_TYPE ulpi 733 734 #ifdef CONFIG_ARCH_B4860 735 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 736 "bank_intlv=cs0_cs1;" \ 737 "en_cpc:cpc2;" 738 #else 739 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 740 #endif 741 742 #define CONFIG_EXTRA_ENV_SETTINGS \ 743 HWCONFIG \ 744 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 745 "netdev=eth0\0" \ 746 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 747 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 748 "tftpflash=tftpboot $loadaddr $uboot && " \ 749 "protect off $ubootaddr +$filesize && " \ 750 "erase $ubootaddr +$filesize && " \ 751 "cp.b $loadaddr $ubootaddr $filesize && " \ 752 "protect on $ubootaddr +$filesize && " \ 753 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 754 "consoledev=ttyS0\0" \ 755 "ramdiskaddr=2000000\0" \ 756 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 757 "fdtaddr=1e00000\0" \ 758 "fdtfile=b4860qds/b4860qds.dtb\0" \ 759 "bdev=sda3\0" 760 761 /* For emulation this causes u-boot to jump to the start of the proof point 762 app code automatically */ 763 #define CONFIG_PROOF_POINTS \ 764 "setenv bootargs root=/dev/$bdev rw " \ 765 "console=$consoledev,$baudrate $othbootargs;" \ 766 "cpu 1 release 0x29000000 - - -;" \ 767 "cpu 2 release 0x29000000 - - -;" \ 768 "cpu 3 release 0x29000000 - - -;" \ 769 "cpu 4 release 0x29000000 - - -;" \ 770 "cpu 5 release 0x29000000 - - -;" \ 771 "cpu 6 release 0x29000000 - - -;" \ 772 "cpu 7 release 0x29000000 - - -;" \ 773 "go 0x29000000" 774 775 #define CONFIG_HVBOOT \ 776 "setenv bootargs config-addr=0x60000000; " \ 777 "bootm 0x01000000 - 0x00f00000" 778 779 #define CONFIG_ALU \ 780 "setenv bootargs root=/dev/$bdev rw " \ 781 "console=$consoledev,$baudrate $othbootargs;" \ 782 "cpu 1 release 0x01000000 - - -;" \ 783 "cpu 2 release 0x01000000 - - -;" \ 784 "cpu 3 release 0x01000000 - - -;" \ 785 "cpu 4 release 0x01000000 - - -;" \ 786 "cpu 5 release 0x01000000 - - -;" \ 787 "cpu 6 release 0x01000000 - - -;" \ 788 "cpu 7 release 0x01000000 - - -;" \ 789 "go 0x01000000" 790 791 #define CONFIG_LINUX \ 792 "setenv bootargs root=/dev/ram rw " \ 793 "console=$consoledev,$baudrate $othbootargs;" \ 794 "setenv ramdiskaddr 0x02000000;" \ 795 "setenv fdtaddr 0x01e00000;" \ 796 "setenv loadaddr 0x1000000;" \ 797 "bootm $loadaddr $ramdiskaddr $fdtaddr" 798 799 #define CONFIG_HDBOOT \ 800 "setenv bootargs root=/dev/$bdev rw " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr - $fdtaddr" 805 806 #define CONFIG_NFSBOOTCOMMAND \ 807 "setenv bootargs root=/dev/nfs rw " \ 808 "nfsroot=$serverip:$rootpath " \ 809 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "tftp $loadaddr $bootfile;" \ 812 "tftp $fdtaddr $fdtfile;" \ 813 "bootm $loadaddr - $fdtaddr" 814 815 #define CONFIG_RAMBOOTCOMMAND \ 816 "setenv bootargs root=/dev/ram rw " \ 817 "console=$consoledev,$baudrate $othbootargs;" \ 818 "tftp $ramdiskaddr $ramdiskfile;" \ 819 "tftp $loadaddr $bootfile;" \ 820 "tftp $fdtaddr $fdtfile;" \ 821 "bootm $loadaddr $ramdiskaddr $fdtaddr" 822 823 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 824 825 #include <asm/fsl_secure_boot.h> 826 827 #endif /* __CONFIG_H */ 828