1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SYS_TEXT_BASE 0x00201000 23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 24 #define CONFIG_SPL_PAD_TO 0x40000 25 #define CONFIG_SPL_MAX_SIZE 0x28000 26 #define RESET_VECTOR_OFFSET 0x27FFC 27 #define BOOT_PAGE_OFFSET 0x27000 28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 33 #define CONFIG_SPL_NAND_BOOT 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #define CONFIG_SYS_NO_FLASH 39 #endif 40 #endif 41 #endif 42 43 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 44 /* Set 1M boot space */ 45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 47 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 48 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 49 #define CONFIG_SYS_NO_FLASH 50 #endif 51 52 /* High Level Configuration Options */ 53 #define CONFIG_BOOKE 54 #define CONFIG_E500 /* BOOKE e500 family */ 55 #define CONFIG_E500MC /* BOOKE e500mc family */ 56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 57 #define CONFIG_MP /* support multiple processors */ 58 59 #ifndef CONFIG_SYS_TEXT_BASE 60 #define CONFIG_SYS_TEXT_BASE 0xeff40000 61 #endif 62 63 #ifndef CONFIG_RESET_VECTOR_ADDRESS 64 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 65 #endif 66 67 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 68 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 69 #define CONFIG_FSL_IFC /* Enable IFC Support */ 70 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 71 #define CONFIG_PCIE1 /* PCIE controller 1 */ 72 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 74 75 #ifndef CONFIG_ARCH_B4420 76 #define CONFIG_SYS_SRIO 77 #define CONFIG_SRIO1 /* SRIO port 1 */ 78 #define CONFIG_SRIO2 /* SRIO port 2 */ 79 #define CONFIG_SRIO_PCIE_BOOT_MASTER 80 #endif 81 82 /* I2C bus multiplexer */ 83 #define I2C_MUX_PCA_ADDR 0x77 84 85 /* VSC Crossbar switches */ 86 #define CONFIG_VSC_CROSSBAR 87 #define I2C_CH_DEFAULT 0x8 88 #define I2C_CH_VSC3316 0xc 89 #define I2C_CH_VSC3308 0xd 90 91 #define VSC3316_TX_ADDRESS 0x70 92 #define VSC3316_RX_ADDRESS 0x71 93 #define VSC3308_TX_ADDRESS 0x02 94 #define VSC3308_RX_ADDRESS 0x03 95 96 /* IDT clock synthesizers */ 97 #define CONFIG_IDT8T49N222A 98 #define I2C_CH_IDT 0x9 99 100 #define IDT_SERDES1_ADDRESS 0x6E 101 #define IDT_SERDES2_ADDRESS 0x6C 102 103 /* Voltage monitor on channel 2*/ 104 #define I2C_MUX_CH_VOL_MONITOR 0xa 105 #define I2C_VOL_MONITOR_ADDR 0x40 106 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 107 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 108 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 109 110 #define CONFIG_ZM7300 111 #define I2C_MUX_CH_DPM 0xa 112 #define I2C_DPM_ADDR 0x28 113 114 #define CONFIG_ENV_OVERWRITE 115 116 #ifdef CONFIG_SYS_NO_FLASH 117 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 118 #define CONFIG_ENV_IS_NOWHERE 119 #endif 120 #else 121 #define CONFIG_FLASH_CFI_DRIVER 122 #define CONFIG_SYS_FLASH_CFI 123 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 124 #endif 125 126 #if defined(CONFIG_SPIFLASH) 127 #define CONFIG_SYS_EXTRA_ENV_RELOC 128 #define CONFIG_ENV_IS_IN_SPI_FLASH 129 #define CONFIG_ENV_SPI_BUS 0 130 #define CONFIG_ENV_SPI_CS 0 131 #define CONFIG_ENV_SPI_MAX_HZ 10000000 132 #define CONFIG_ENV_SPI_MODE 0 133 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 134 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 135 #define CONFIG_ENV_SECT_SIZE 0x10000 136 #elif defined(CONFIG_SDCARD) 137 #define CONFIG_SYS_EXTRA_ENV_RELOC 138 #define CONFIG_ENV_IS_IN_MMC 139 #define CONFIG_SYS_MMC_ENV_DEV 0 140 #define CONFIG_ENV_SIZE 0x2000 141 #define CONFIG_ENV_OFFSET (512 * 1097) 142 #elif defined(CONFIG_NAND) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_NAND 145 #define CONFIG_ENV_SIZE 0x2000 146 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 147 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 148 #define CONFIG_ENV_IS_IN_REMOTE 149 #define CONFIG_ENV_ADDR 0xffe20000 150 #define CONFIG_ENV_SIZE 0x2000 151 #elif defined(CONFIG_ENV_IS_NOWHERE) 152 #define CONFIG_ENV_SIZE 0x2000 153 #else 154 #define CONFIG_ENV_IS_IN_FLASH 155 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 156 #define CONFIG_ENV_SIZE 0x2000 157 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 158 #endif 159 160 #ifndef __ASSEMBLY__ 161 unsigned long get_board_sys_clk(void); 162 unsigned long get_board_ddr_clk(void); 163 #endif 164 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 165 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 166 167 /* 168 * These can be toggled for performance analysis, otherwise use default. 169 */ 170 #define CONFIG_SYS_CACHE_STASHING 171 #define CONFIG_BTB /* toggle branch predition */ 172 #define CONFIG_DDR_ECC 173 #ifdef CONFIG_DDR_ECC 174 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 175 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 176 #endif 177 178 #define CONFIG_ENABLE_36BIT_PHYS 179 180 #ifdef CONFIG_PHYS_64BIT 181 #define CONFIG_ADDR_MAP 182 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 183 #endif 184 185 #if 0 186 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 187 #endif 188 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 189 #define CONFIG_SYS_MEMTEST_END 0x00400000 190 #define CONFIG_SYS_ALT_MEMTEST 191 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 192 193 /* 194 * Config the L3 Cache as L3 SRAM 195 */ 196 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 197 #define CONFIG_SYS_L3_SIZE 256 << 10 198 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 199 #ifdef CONFIG_NAND 200 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 201 #endif 202 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 203 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 204 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 205 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 206 207 #ifdef CONFIG_PHYS_64BIT 208 #define CONFIG_SYS_DCSRBAR 0xf0000000 209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 210 #endif 211 212 /* EEPROM */ 213 #define CONFIG_ID_EEPROM 214 #define CONFIG_SYS_I2C_EEPROM_NXID 215 #define CONFIG_SYS_EEPROM_BUS_NUM 0 216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 220 221 /* 222 * DDR Setup 223 */ 224 #define CONFIG_VERY_BIG_RAM 225 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 226 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 227 228 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 229 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 230 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 231 232 #define CONFIG_DDR_SPD 233 #define CONFIG_SYS_DDR_RAW_TIMING 234 #define CONFIG_SYS_FSL_DDR3 235 #ifndef CONFIG_SPL_BUILD 236 #define CONFIG_FSL_DDR_INTERACTIVE 237 #endif 238 239 #define CONFIG_SYS_SPD_BUS_NUM 0 240 #define SPD_EEPROM_ADDRESS1 0x51 241 #define SPD_EEPROM_ADDRESS2 0x53 242 243 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 244 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 245 246 /* 247 * IFC Definitions 248 */ 249 #define CONFIG_SYS_FLASH_BASE 0xe0000000 250 #ifdef CONFIG_PHYS_64BIT 251 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 252 #else 253 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 254 #endif 255 256 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 257 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 258 + 0x8000000) | \ 259 CSPR_PORT_SIZE_16 | \ 260 CSPR_MSEL_NOR | \ 261 CSPR_V) 262 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 263 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 264 CSPR_PORT_SIZE_16 | \ 265 CSPR_MSEL_NOR | \ 266 CSPR_V) 267 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 268 /* NOR Flash Timing Params */ 269 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 270 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 271 FTIM0_NOR_TEADC(0x04) | \ 272 FTIM0_NOR_TEAHC(0x20)) 273 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 274 FTIM1_NOR_TRAD_NOR(0x1A) |\ 275 FTIM1_NOR_TSEQRAD_NOR(0x13)) 276 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 277 FTIM2_NOR_TCH(0x0E) | \ 278 FTIM2_NOR_TWPH(0x0E) | \ 279 FTIM2_NOR_TWP(0x1c)) 280 #define CONFIG_SYS_NOR_FTIM3 0x0 281 282 #define CONFIG_SYS_FLASH_QUIET_TEST 283 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 284 285 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 286 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 287 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 288 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 289 290 #define CONFIG_SYS_FLASH_EMPTY_INFO 291 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 292 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 293 294 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 295 #define CONFIG_FSL_QIXIS_V2 296 #define QIXIS_BASE 0xffdf0000 297 #ifdef CONFIG_PHYS_64BIT 298 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 299 #else 300 #define QIXIS_BASE_PHYS QIXIS_BASE 301 #endif 302 #define QIXIS_LBMAP_SWITCH 0x01 303 #define QIXIS_LBMAP_MASK 0x0f 304 #define QIXIS_LBMAP_SHIFT 0 305 #define QIXIS_LBMAP_DFLTBANK 0x00 306 #define QIXIS_LBMAP_ALTBANK 0x02 307 #define QIXIS_RST_CTL_RESET 0x31 308 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 309 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 310 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 311 312 #define CONFIG_SYS_CSPR3_EXT (0xf) 313 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 314 | CSPR_PORT_SIZE_8 \ 315 | CSPR_MSEL_GPCM \ 316 | CSPR_V) 317 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 318 #define CONFIG_SYS_CSOR3 0x0 319 /* QIXIS Timing parameters for IFC CS3 */ 320 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 321 FTIM0_GPCM_TEADC(0x0e) | \ 322 FTIM0_GPCM_TEAHC(0x0e)) 323 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 324 FTIM1_GPCM_TRAD(0x1f)) 325 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 326 FTIM2_GPCM_TCH(0x8) | \ 327 FTIM2_GPCM_TWP(0x1f)) 328 #define CONFIG_SYS_CS3_FTIM3 0x0 329 330 /* NAND Flash on IFC */ 331 #define CONFIG_NAND_FSL_IFC 332 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 333 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 334 #define CONFIG_SYS_NAND_BASE 0xff800000 335 #ifdef CONFIG_PHYS_64BIT 336 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 337 #else 338 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 339 #endif 340 341 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 342 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 343 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 344 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 345 | CSPR_V) 346 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 347 348 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 349 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 350 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 351 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 352 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 353 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 354 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 355 356 #define CONFIG_SYS_NAND_ONFI_DETECTION 357 358 /* ONFI NAND Flash mode0 Timing Params */ 359 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 360 FTIM0_NAND_TWP(0x18) | \ 361 FTIM0_NAND_TWCHT(0x07) | \ 362 FTIM0_NAND_TWH(0x0a)) 363 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 364 FTIM1_NAND_TWBE(0x39) | \ 365 FTIM1_NAND_TRR(0x0e) | \ 366 FTIM1_NAND_TRP(0x18)) 367 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 368 FTIM2_NAND_TREH(0x0a) | \ 369 FTIM2_NAND_TWHRE(0x1e)) 370 #define CONFIG_SYS_NAND_FTIM3 0x0 371 372 #define CONFIG_SYS_NAND_DDR_LAW 11 373 374 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 375 #define CONFIG_SYS_MAX_NAND_DEVICE 1 376 #define CONFIG_CMD_NAND 377 378 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 379 380 #if defined(CONFIG_NAND) 381 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 382 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 383 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 384 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 385 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 386 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 387 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 388 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 389 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 390 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 391 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 392 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 393 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 394 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 395 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 396 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 397 #else 398 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 399 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 400 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 401 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 402 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 403 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 404 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 405 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 406 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 407 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 408 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 409 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 410 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 411 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 412 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 413 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 414 #endif 415 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 423 424 #ifdef CONFIG_SPL_BUILD 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 426 #else 427 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 428 #endif 429 430 #if defined(CONFIG_RAMBOOT_PBL) 431 #define CONFIG_SYS_RAMBOOT 432 #endif 433 434 #define CONFIG_BOARD_EARLY_INIT_R 435 #define CONFIG_MISC_INIT_R 436 437 #define CONFIG_HWCONFIG 438 439 /* define to use L1 as initial stack */ 440 #define CONFIG_L1_INIT_RAM 441 #define CONFIG_SYS_INIT_RAM_LOCK 442 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 446 /* The assembler doesn't like typecast */ 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 448 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 449 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 450 #else 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 454 #endif 455 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 456 457 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 458 GENERATED_GBL_DATA_SIZE) 459 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 460 461 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 462 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 463 464 /* Serial Port - controlled on board with jumper J8 465 * open - index 2 466 * shorted - index 1 467 */ 468 #define CONFIG_CONS_INDEX 1 469 #define CONFIG_SYS_NS16550_SERIAL 470 #define CONFIG_SYS_NS16550_REG_SIZE 1 471 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 472 473 #define CONFIG_SYS_BAUDRATE_TABLE \ 474 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 475 476 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 477 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 478 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 479 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 480 481 /* I2C */ 482 #define CONFIG_SYS_I2C 483 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 484 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 485 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 486 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 487 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 488 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 489 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 490 491 /* 492 * RTC configuration 493 */ 494 #define RTC 495 #define CONFIG_RTC_DS3231 1 496 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 497 498 /* 499 * RapidIO 500 */ 501 #ifdef CONFIG_SYS_SRIO 502 #ifdef CONFIG_SRIO1 503 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 504 #ifdef CONFIG_PHYS_64BIT 505 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 506 #else 507 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 508 #endif 509 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 510 #endif 511 512 #ifdef CONFIG_SRIO2 513 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 514 #ifdef CONFIG_PHYS_64BIT 515 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 516 #else 517 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 518 #endif 519 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 520 #endif 521 #endif 522 523 /* 524 * for slave u-boot IMAGE instored in master memory space, 525 * PHYS must be aligned based on the SIZE 526 */ 527 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 528 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 529 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 530 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 531 /* 532 * for slave UCODE and ENV instored in master memory space, 533 * PHYS must be aligned based on the SIZE 534 */ 535 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 536 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 537 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 538 539 /* slave core release by master*/ 540 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 541 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 542 543 /* 544 * SRIO_PCIE_BOOT - SLAVE 545 */ 546 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 547 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 548 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 549 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 550 #endif 551 552 /* 553 * eSPI - Enhanced SPI 554 */ 555 #define CONFIG_SF_DEFAULT_SPEED 10000000 556 #define CONFIG_SF_DEFAULT_MODE 0 557 558 /* 559 * MAPLE 560 */ 561 #ifdef CONFIG_PHYS_64BIT 562 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 563 #else 564 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 565 #endif 566 567 /* 568 * General PCI 569 * Memory space is mapped 1-1, but I/O space must start from 0. 570 */ 571 572 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 573 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 574 #ifdef CONFIG_PHYS_64BIT 575 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 576 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 577 #else 578 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 579 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 580 #endif 581 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 582 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 583 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 584 #ifdef CONFIG_PHYS_64BIT 585 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 586 #else 587 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 588 #endif 589 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 590 591 /* Qman/Bman */ 592 #ifndef CONFIG_NOBQFMAN 593 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 594 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 595 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 596 #ifdef CONFIG_PHYS_64BIT 597 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 598 #else 599 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 600 #endif 601 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 602 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 603 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 604 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 605 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 606 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 607 CONFIG_SYS_BMAN_CENA_SIZE) 608 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 609 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 610 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 611 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 614 #else 615 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 616 #endif 617 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 618 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 619 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 620 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 621 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 623 CONFIG_SYS_QMAN_CENA_SIZE) 624 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 626 627 #define CONFIG_SYS_DPAA_FMAN 628 629 #define CONFIG_SYS_DPAA_RMAN 630 631 /* Default address of microcode for the Linux Fman driver */ 632 #if defined(CONFIG_SPIFLASH) 633 /* 634 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 635 * env, so we got 0x110000. 636 */ 637 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 638 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 639 #elif defined(CONFIG_SDCARD) 640 /* 641 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 642 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 643 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 644 */ 645 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 646 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 647 #elif defined(CONFIG_NAND) 648 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 649 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 650 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 651 /* 652 * Slave has no ucode locally, it can fetch this from remote. When implementing 653 * in two corenet boards, slave's ucode could be stored in master's memory 654 * space, the address can be mapped from slave TLB->slave LAW-> 655 * slave SRIO or PCIE outbound window->master inbound window-> 656 * master LAW->the ucode address in master's memory space. 657 */ 658 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 659 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 660 #else 661 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 662 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 663 #endif 664 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 665 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 666 #endif /* CONFIG_NOBQFMAN */ 667 668 #ifdef CONFIG_SYS_DPAA_FMAN 669 #define CONFIG_FMAN_ENET 670 #define CONFIG_PHYLIB_10G 671 #define CONFIG_PHY_VITESSE 672 #define CONFIG_PHY_TERANETICS 673 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 674 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 675 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 676 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 677 #endif 678 679 #ifdef CONFIG_PCI 680 #define CONFIG_PCI_INDIRECT_BRIDGE 681 682 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 683 #define CONFIG_DOS_PARTITION 684 #endif /* CONFIG_PCI */ 685 686 #ifdef CONFIG_FMAN_ENET 687 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 688 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 689 690 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 691 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 692 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 693 694 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 695 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 696 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 697 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 698 699 #define CONFIG_MII /* MII PHY management */ 700 #define CONFIG_ETHPRIME "FM1@DTSEC1" 701 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 702 #endif 703 704 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 705 706 /* 707 * Environment 708 */ 709 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 710 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 711 712 /* 713 * Command line configuration. 714 */ 715 #define CONFIG_CMD_DATE 716 #define CONFIG_CMD_EEPROM 717 #define CONFIG_CMD_ERRATA 718 #define CONFIG_CMD_IRQ 719 #define CONFIG_CMD_REGINFO 720 721 #ifdef CONFIG_PCI 722 #define CONFIG_CMD_PCI 723 #endif 724 725 /* Hash command with SHA acceleration supported in hardware */ 726 #ifdef CONFIG_FSL_CAAM 727 #define CONFIG_CMD_HASH 728 #define CONFIG_SHA_HW_ACCEL 729 #endif 730 731 /* 732 * USB 733 */ 734 #define CONFIG_HAS_FSL_DR_USB 735 736 #ifdef CONFIG_HAS_FSL_DR_USB 737 #define CONFIG_USB_EHCI 738 739 #ifdef CONFIG_USB_EHCI 740 #define CONFIG_USB_EHCI_FSL 741 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 742 #endif 743 #endif 744 745 /* 746 * Miscellaneous configurable options 747 */ 748 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 749 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 750 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 751 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 752 #ifdef CONFIG_CMD_KGDB 753 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 754 #else 755 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 756 #endif 757 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 758 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 759 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 760 761 /* 762 * For booting Linux, the board info and command line data 763 * have to be in the first 64 MB of memory, since this is 764 * the maximum mapped by the Linux kernel during initialization. 765 */ 766 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 767 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 768 769 #ifdef CONFIG_CMD_KGDB 770 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 771 #endif 772 773 /* 774 * Environment Configuration 775 */ 776 #define CONFIG_ROOTPATH "/opt/nfsroot" 777 #define CONFIG_BOOTFILE "uImage" 778 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 779 780 /* default location for tftp and bootm */ 781 #define CONFIG_LOADADDR 1000000 782 783 784 #define CONFIG_BAUDRATE 115200 785 786 #define __USB_PHY_TYPE ulpi 787 788 #ifdef CONFIG_ARCH_B4860 789 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 790 "bank_intlv=cs0_cs1;" \ 791 "en_cpc:cpc2;" 792 #else 793 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 794 #endif 795 796 #define CONFIG_EXTRA_ENV_SETTINGS \ 797 HWCONFIG \ 798 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 799 "netdev=eth0\0" \ 800 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 801 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 802 "tftpflash=tftpboot $loadaddr $uboot && " \ 803 "protect off $ubootaddr +$filesize && " \ 804 "erase $ubootaddr +$filesize && " \ 805 "cp.b $loadaddr $ubootaddr $filesize && " \ 806 "protect on $ubootaddr +$filesize && " \ 807 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 808 "consoledev=ttyS0\0" \ 809 "ramdiskaddr=2000000\0" \ 810 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 811 "fdtaddr=1e00000\0" \ 812 "fdtfile=b4860qds/b4860qds.dtb\0" \ 813 "bdev=sda3\0" 814 815 /* For emulation this causes u-boot to jump to the start of the proof point 816 app code automatically */ 817 #define CONFIG_PROOF_POINTS \ 818 "setenv bootargs root=/dev/$bdev rw " \ 819 "console=$consoledev,$baudrate $othbootargs;" \ 820 "cpu 1 release 0x29000000 - - -;" \ 821 "cpu 2 release 0x29000000 - - -;" \ 822 "cpu 3 release 0x29000000 - - -;" \ 823 "cpu 4 release 0x29000000 - - -;" \ 824 "cpu 5 release 0x29000000 - - -;" \ 825 "cpu 6 release 0x29000000 - - -;" \ 826 "cpu 7 release 0x29000000 - - -;" \ 827 "go 0x29000000" 828 829 #define CONFIG_HVBOOT \ 830 "setenv bootargs config-addr=0x60000000; " \ 831 "bootm 0x01000000 - 0x00f00000" 832 833 #define CONFIG_ALU \ 834 "setenv bootargs root=/dev/$bdev rw " \ 835 "console=$consoledev,$baudrate $othbootargs;" \ 836 "cpu 1 release 0x01000000 - - -;" \ 837 "cpu 2 release 0x01000000 - - -;" \ 838 "cpu 3 release 0x01000000 - - -;" \ 839 "cpu 4 release 0x01000000 - - -;" \ 840 "cpu 5 release 0x01000000 - - -;" \ 841 "cpu 6 release 0x01000000 - - -;" \ 842 "cpu 7 release 0x01000000 - - -;" \ 843 "go 0x01000000" 844 845 #define CONFIG_LINUX \ 846 "setenv bootargs root=/dev/ram rw " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "setenv ramdiskaddr 0x02000000;" \ 849 "setenv fdtaddr 0x01e00000;" \ 850 "setenv loadaddr 0x1000000;" \ 851 "bootm $loadaddr $ramdiskaddr $fdtaddr" 852 853 #define CONFIG_HDBOOT \ 854 "setenv bootargs root=/dev/$bdev rw " \ 855 "console=$consoledev,$baudrate $othbootargs;" \ 856 "tftp $loadaddr $bootfile;" \ 857 "tftp $fdtaddr $fdtfile;" \ 858 "bootm $loadaddr - $fdtaddr" 859 860 #define CONFIG_NFSBOOTCOMMAND \ 861 "setenv bootargs root=/dev/nfs rw " \ 862 "nfsroot=$serverip:$rootpath " \ 863 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "tftp $loadaddr $bootfile;" \ 866 "tftp $fdtaddr $fdtfile;" \ 867 "bootm $loadaddr - $fdtaddr" 868 869 #define CONFIG_RAMBOOTCOMMAND \ 870 "setenv bootargs root=/dev/ram rw " \ 871 "console=$consoledev,$baudrate $othbootargs;" \ 872 "tftp $ramdiskaddr $ramdiskfile;" \ 873 "tftp $loadaddr $bootfile;" \ 874 "tftp $fdtaddr $fdtfile;" \ 875 "bootm $loadaddr $ramdiskaddr $fdtaddr" 876 877 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 878 879 #include <asm/fsl_secure_boot.h> 880 881 #endif /* __CONFIG_H */ 882