xref: /openbmc/u-boot/include/configs/B4860QDS.h (revision 66c433ed4342e5761ee9b048c85fe47d31130b2e)
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * Copyright 2011-2012 Freescale Semiconductor, Inc.
4   */
5  
6  #ifndef __CONFIG_H
7  #define __CONFIG_H
8  
9  /*
10   * B4860 QDS board configuration file
11   */
12  #ifdef CONFIG_RAMBOOT_PBL
13  #define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
14  #define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
15  #ifndef CONFIG_NAND
16  #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
17  #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
18  #else
19  #define CONFIG_SPL_FLUSH_IMAGE
20  #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
21  #define CONFIG_SPL_PAD_TO		0x40000
22  #define CONFIG_SPL_MAX_SIZE		0x28000
23  #define RESET_VECTOR_OFFSET		0x27FFC
24  #define BOOT_PAGE_OFFSET		0x27000
25  #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
26  #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
27  #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
28  #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
29  #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
30  #define CONFIG_SPL_NAND_BOOT
31  #ifdef CONFIG_SPL_BUILD
32  #define CONFIG_SPL_SKIP_RELOCATE
33  #define CONFIG_SPL_COMMON_INIT_DDR
34  #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
35  #endif
36  #endif
37  #endif
38  
39  #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
40  /* Set 1M boot space */
41  #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42  #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43  		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44  #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
45  #endif
46  
47  /* High Level Configuration Options */
48  #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
49  
50  #ifndef CONFIG_RESET_VECTOR_ADDRESS
51  #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
52  #endif
53  
54  #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
55  #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
56  #define CONFIG_PCIE1			/* PCIE controller 1 */
57  #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
58  #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
59  
60  #ifndef CONFIG_ARCH_B4420
61  #define CONFIG_SYS_SRIO
62  #define CONFIG_SRIO1			/* SRIO port 1 */
63  #define CONFIG_SRIO2			/* SRIO port 2 */
64  #define CONFIG_SRIO_PCIE_BOOT_MASTER
65  #endif
66  
67  /* I2C bus multiplexer */
68  #define I2C_MUX_PCA_ADDR                0x77
69  
70  /* VSC Crossbar switches */
71  #define CONFIG_VSC_CROSSBAR
72  #define I2C_CH_DEFAULT                  0x8
73  #define I2C_CH_VSC3316                  0xc
74  #define I2C_CH_VSC3308                  0xd
75  
76  #define VSC3316_TX_ADDRESS              0x70
77  #define VSC3316_RX_ADDRESS              0x71
78  #define VSC3308_TX_ADDRESS              0x02
79  #define VSC3308_RX_ADDRESS              0x03
80  
81  /* IDT clock synthesizers */
82  #define CONFIG_IDT8T49N222A
83  #define I2C_CH_IDT                     0x9
84  
85  #define IDT_SERDES1_ADDRESS            0x6E
86  #define IDT_SERDES2_ADDRESS            0x6C
87  
88  /* Voltage monitor on channel 2*/
89  #define I2C_MUX_CH_VOL_MONITOR		0xa
90  #define I2C_VOL_MONITOR_ADDR		0x40
91  #define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
92  #define I2C_VOL_MONITOR_BUS_V_OVF	0x1
93  #define I2C_VOL_MONITOR_BUS_V_SHIFT	3
94  
95  #define CONFIG_ZM7300
96  #define I2C_MUX_CH_DPM			0xa
97  #define I2C_DPM_ADDR			0x28
98  
99  #define CONFIG_ENV_OVERWRITE
100  
101  #if defined(CONFIG_SPIFLASH)
102  #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
103  #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
104  #define CONFIG_ENV_SECT_SIZE            0x10000
105  #elif defined(CONFIG_SDCARD)
106  #define CONFIG_SYS_MMC_ENV_DEV          0
107  #define CONFIG_ENV_SIZE			0x2000
108  #define CONFIG_ENV_OFFSET		(512 * 1097)
109  #elif defined(CONFIG_NAND)
110  #define CONFIG_ENV_SIZE			0x2000
111  #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
112  #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
113  #define CONFIG_ENV_ADDR		0xffe20000
114  #define CONFIG_ENV_SIZE		0x2000
115  #elif defined(CONFIG_ENV_IS_NOWHERE)
116  #define CONFIG_ENV_SIZE		0x2000
117  #else
118  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
119  #define CONFIG_ENV_SIZE		0x2000
120  #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
121  #endif
122  
123  #ifndef __ASSEMBLY__
124  unsigned long get_board_sys_clk(void);
125  unsigned long get_board_ddr_clk(void);
126  #endif
127  #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
128  #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
129  
130  /*
131   * These can be toggled for performance analysis, otherwise use default.
132   */
133  #define CONFIG_SYS_CACHE_STASHING
134  #define CONFIG_BTB			/* toggle branch predition */
135  #define CONFIG_DDR_ECC
136  #ifdef CONFIG_DDR_ECC
137  #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
138  #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
139  #endif
140  
141  #define CONFIG_ENABLE_36BIT_PHYS
142  
143  #ifdef CONFIG_PHYS_64BIT
144  #define CONFIG_ADDR_MAP
145  #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
146  #endif
147  
148  #if 0
149  #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
150  #endif
151  #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
152  #define CONFIG_SYS_MEMTEST_END		0x00400000
153  
154  /*
155   *  Config the L3 Cache as L3 SRAM
156   */
157  #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
158  #define CONFIG_SYS_L3_SIZE		256 << 10
159  #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
160  #ifdef CONFIG_NAND
161  #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
162  #endif
163  #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
164  #define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
165  #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
166  
167  #ifdef CONFIG_PHYS_64BIT
168  #define CONFIG_SYS_DCSRBAR		0xf0000000
169  #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
170  #endif
171  
172  /* EEPROM */
173  #define CONFIG_ID_EEPROM
174  #define CONFIG_SYS_I2C_EEPROM_NXID
175  #define CONFIG_SYS_EEPROM_BUS_NUM	0
176  #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
177  #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
178  #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
179  #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
180  
181  /*
182   * DDR Setup
183   */
184  #define CONFIG_VERY_BIG_RAM
185  #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
186  #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
187  
188  #define CONFIG_DIMM_SLOTS_PER_CTLR	1
189  #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
190  
191  #define CONFIG_DDR_SPD
192  #define CONFIG_SYS_DDR_RAW_TIMING
193  
194  #define CONFIG_SYS_SPD_BUS_NUM	0
195  #define SPD_EEPROM_ADDRESS1	0x51
196  #define SPD_EEPROM_ADDRESS2	0x53
197  
198  #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
199  #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
200  
201  /*
202   * IFC Definitions
203   */
204  #define CONFIG_SYS_FLASH_BASE	0xe0000000
205  #ifdef CONFIG_PHYS_64BIT
206  #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
207  #else
208  #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
209  #endif
210  
211  #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
212  #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
213  				+ 0x8000000) | \
214  				CSPR_PORT_SIZE_16 | \
215  				CSPR_MSEL_NOR | \
216  				CSPR_V)
217  #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
218  #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
219  				CSPR_PORT_SIZE_16 | \
220  				CSPR_MSEL_NOR | \
221  				CSPR_V)
222  #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128 * 1024 * 1024)
223  /* NOR Flash Timing Params */
224  #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
225  #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
226  				FTIM0_NOR_TEADC(0x04) | \
227  				FTIM0_NOR_TEAHC(0x20))
228  #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
229  				FTIM1_NOR_TRAD_NOR(0x1A) |\
230  				FTIM1_NOR_TSEQRAD_NOR(0x13))
231  #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
232  				FTIM2_NOR_TCH(0x0E) | \
233  				FTIM2_NOR_TWPH(0x0E) | \
234  				FTIM2_NOR_TWP(0x1c))
235  #define CONFIG_SYS_NOR_FTIM3	0x0
236  
237  #define CONFIG_SYS_FLASH_QUIET_TEST
238  #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
239  
240  #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
241  #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
242  #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
243  #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
244  
245  #define CONFIG_SYS_FLASH_EMPTY_INFO
246  #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
247  					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
248  
249  #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
250  #define CONFIG_FSL_QIXIS_V2
251  #define QIXIS_BASE		0xffdf0000
252  #ifdef CONFIG_PHYS_64BIT
253  #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
254  #else
255  #define QIXIS_BASE_PHYS		QIXIS_BASE
256  #endif
257  #define QIXIS_LBMAP_SWITCH		0x01
258  #define QIXIS_LBMAP_MASK		0x0f
259  #define QIXIS_LBMAP_SHIFT		0
260  #define QIXIS_LBMAP_DFLTBANK		0x00
261  #define QIXIS_LBMAP_ALTBANK		0x02
262  #define QIXIS_RST_CTL_RESET		0x31
263  #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
264  #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
265  #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
266  
267  #define CONFIG_SYS_CSPR3_EXT	(0xf)
268  #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
269  				| CSPR_PORT_SIZE_8 \
270  				| CSPR_MSEL_GPCM \
271  				| CSPR_V)
272  #define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
273  #define CONFIG_SYS_CSOR3	0x0
274  /* QIXIS Timing parameters for IFC CS3 */
275  #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
276  					FTIM0_GPCM_TEADC(0x0e) | \
277  					FTIM0_GPCM_TEAHC(0x0e))
278  #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
279  					FTIM1_GPCM_TRAD(0x1f))
280  #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
281  					FTIM2_GPCM_TCH(0x8) | \
282  					FTIM2_GPCM_TWP(0x1f))
283  #define CONFIG_SYS_CS3_FTIM3		0x0
284  
285  /* NAND Flash on IFC */
286  #define CONFIG_NAND_FSL_IFC
287  #define CONFIG_SYS_NAND_MAX_ECCPOS	256
288  #define CONFIG_SYS_NAND_MAX_OOBFREE	2
289  #define CONFIG_SYS_NAND_BASE		0xff800000
290  #ifdef CONFIG_PHYS_64BIT
291  #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
292  #else
293  #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
294  #endif
295  
296  #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
297  #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
298  				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
299  				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
300  				| CSPR_V)
301  #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
302  
303  #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
304  				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
305  				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
306  				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
307  				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
308  				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
309  				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
310  
311  #define CONFIG_SYS_NAND_ONFI_DETECTION
312  
313  /* ONFI NAND Flash mode0 Timing Params */
314  #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
315  					FTIM0_NAND_TWP(0x18)   | \
316  					FTIM0_NAND_TWCHT(0x07) | \
317  					FTIM0_NAND_TWH(0x0a))
318  #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
319  					FTIM1_NAND_TWBE(0x39)  | \
320  					FTIM1_NAND_TRR(0x0e)   | \
321  					FTIM1_NAND_TRP(0x18))
322  #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
323  					FTIM2_NAND_TREH(0x0a) | \
324  					FTIM2_NAND_TWHRE(0x1e))
325  #define CONFIG_SYS_NAND_FTIM3		0x0
326  
327  #define CONFIG_SYS_NAND_DDR_LAW		11
328  
329  #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
330  #define CONFIG_SYS_MAX_NAND_DEVICE	1
331  
332  #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
333  
334  #if defined(CONFIG_NAND)
335  #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
336  #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
337  #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
338  #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
339  #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
340  #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
341  #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
342  #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
343  #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
344  #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
345  #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
346  #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
347  #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
348  #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
349  #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
350  #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
351  #else
352  #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
353  #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
354  #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
355  #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
356  #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
357  #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
358  #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
359  #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
360  #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
361  #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
362  #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
363  #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
364  #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
365  #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
366  #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
367  #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
368  #endif
369  #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
370  #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
371  #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
372  #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
373  #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
374  #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
375  #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
376  #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
377  
378  #ifdef CONFIG_SPL_BUILD
379  #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
380  #else
381  #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
382  #endif
383  
384  #if defined(CONFIG_RAMBOOT_PBL)
385  #define CONFIG_SYS_RAMBOOT
386  #endif
387  
388  #define CONFIG_HWCONFIG
389  
390  /* define to use L1 as initial stack */
391  #define CONFIG_L1_INIT_RAM
392  #define CONFIG_SYS_INIT_RAM_LOCK
393  #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
394  #ifdef CONFIG_PHYS_64BIT
395  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
396  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
397  /* The assembler doesn't like typecast */
398  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
399  	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
400  	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
401  #else
402  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
403  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
404  #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
405  #endif
406  #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
407  
408  #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
409  					GENERATED_GBL_DATA_SIZE)
410  #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
411  
412  #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
413  #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
414  
415  /* Serial Port - controlled on board with jumper J8
416   * open - index 2
417   * shorted - index 1
418   */
419  #define CONFIG_SYS_NS16550_SERIAL
420  #define CONFIG_SYS_NS16550_REG_SIZE	1
421  #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
422  
423  #define CONFIG_SYS_BAUDRATE_TABLE	\
424  	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
425  
426  #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
427  #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
428  #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
429  #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
430  
431  /* I2C */
432  #define CONFIG_SYS_I2C
433  #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
434  #define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
435  #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
436  #define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
437  #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
438  #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
439  #define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
440  
441  /*
442   * RTC configuration
443   */
444  #define RTC
445  #define CONFIG_RTC_DS3231               1
446  #define CONFIG_SYS_I2C_RTC_ADDR         0x68
447  
448  /*
449   * RapidIO
450   */
451  #ifdef CONFIG_SYS_SRIO
452  #ifdef CONFIG_SRIO1
453  #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
454  #ifdef CONFIG_PHYS_64BIT
455  #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
456  #else
457  #define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
458  #endif
459  #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
460  #endif
461  
462  #ifdef CONFIG_SRIO2
463  #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
464  #ifdef CONFIG_PHYS_64BIT
465  #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
466  #else
467  #define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
468  #endif
469  #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
470  #endif
471  #endif
472  
473  /*
474   * for slave u-boot IMAGE instored in master memory space,
475   * PHYS must be aligned based on the SIZE
476   */
477  #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
478  #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
479  #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
480  #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
481  /*
482   * for slave UCODE and ENV instored in master memory space,
483   * PHYS must be aligned based on the SIZE
484   */
485  #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
486  #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
487  #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
488  
489  /* slave core release by master*/
490  #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
491  #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
492  
493  /*
494   * SRIO_PCIE_BOOT - SLAVE
495   */
496  #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
497  #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
498  #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
499  		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
500  #endif
501  
502  /*
503   * eSPI - Enhanced SPI
504   */
505  
506  /*
507   * MAPLE
508   */
509  #ifdef CONFIG_PHYS_64BIT
510  #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
511  #else
512  #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
513  #endif
514  
515  /*
516   * General PCI
517   * Memory space is mapped 1-1, but I/O space must start from 0.
518   */
519  
520  /* controller 1, direct to uli, tgtid 3, Base address 20000 */
521  #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
522  #ifdef CONFIG_PHYS_64BIT
523  #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
524  #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
525  #else
526  #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
527  #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
528  #endif
529  #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
530  #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
531  #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
532  #ifdef CONFIG_PHYS_64BIT
533  #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
534  #else
535  #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
536  #endif
537  #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
538  
539  /* Qman/Bman */
540  #ifndef CONFIG_NOBQFMAN
541  #define CONFIG_SYS_BMAN_NUM_PORTALS	25
542  #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
543  #ifdef CONFIG_PHYS_64BIT
544  #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
545  #else
546  #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
547  #endif
548  #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
549  #define CONFIG_SYS_BMAN_SP_CENA_SIZE	0x4000
550  #define CONFIG_SYS_BMAN_SP_CINH_SIZE	0x1000
551  #define CONFIG_SYS_BMAN_CENA_BASE	CONFIG_SYS_BMAN_MEM_BASE
552  #define CONFIG_SYS_BMAN_CENA_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
553  #define CONFIG_SYS_BMAN_CINH_BASE	(CONFIG_SYS_BMAN_MEM_BASE + \
554  					CONFIG_SYS_BMAN_CENA_SIZE)
555  #define CONFIG_SYS_BMAN_CINH_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
556  #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
557  #define CONFIG_SYS_QMAN_NUM_PORTALS	25
558  #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
559  #ifdef CONFIG_PHYS_64BIT
560  #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
561  #else
562  #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
563  #endif
564  #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
565  #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
566  #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
567  #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
568  #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
569  #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
570  					CONFIG_SYS_QMAN_CENA_SIZE)
571  #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
572  #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
573  
574  #define CONFIG_SYS_DPAA_FMAN
575  
576  #define CONFIG_SYS_DPAA_RMAN
577  
578  /* Default address of microcode for the Linux Fman driver */
579  #if defined(CONFIG_SPIFLASH)
580  /*
581   * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
582   * env, so we got 0x110000.
583   */
584  #define CONFIG_SYS_QE_FW_IN_SPIFLASH
585  #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
586  #elif defined(CONFIG_SDCARD)
587  /*
588   * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
589   * about 545KB (1089 blocks), Env is stored after the image, and the env size is
590   * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
591   */
592  #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
593  #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
594  #elif defined(CONFIG_NAND)
595  #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
596  #define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
597  #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
598  /*
599   * Slave has no ucode locally, it can fetch this from remote. When implementing
600   * in two corenet boards, slave's ucode could be stored in master's memory
601   * space, the address can be mapped from slave TLB->slave LAW->
602   * slave SRIO or PCIE outbound window->master inbound window->
603   * master LAW->the ucode address in master's memory space.
604   */
605  #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
606  #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
607  #else
608  #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
609  #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
610  #endif
611  #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
612  #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
613  #endif /* CONFIG_NOBQFMAN */
614  
615  #ifdef CONFIG_SYS_DPAA_FMAN
616  #define CONFIG_FMAN_ENET
617  #define CONFIG_PHYLIB_10G
618  #define CONFIG_PHY_VITESSE
619  #define CONFIG_PHY_TERANETICS
620  #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
621  #define SGMII_CARD_PORT2_PHY_ADDR 0x10
622  #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
623  #define SGMII_CARD_PORT4_PHY_ADDR 0x11
624  #endif
625  
626  #ifdef CONFIG_PCI
627  #define CONFIG_PCI_INDIRECT_BRIDGE
628  
629  #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
630  #endif	/* CONFIG_PCI */
631  
632  #ifdef CONFIG_FMAN_ENET
633  #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
634  #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
635  
636  /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
637  #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
638  #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
639  
640  #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
641  #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
642  #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
643  #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
644  
645  #define CONFIG_ETHPRIME		"FM1@DTSEC1"
646  #endif
647  
648  #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
649  
650  /*
651   * Environment
652   */
653  #define CONFIG_LOADS_ECHO		/* echo on for serial download */
654  #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
655  
656  /*
657  * USB
658  */
659  #define CONFIG_HAS_FSL_DR_USB
660  
661  #ifdef CONFIG_HAS_FSL_DR_USB
662  #ifdef CONFIG_USB_EHCI_HCD
663  #define CONFIG_USB_EHCI_FSL
664  #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
665  #endif
666  #endif
667  
668  /*
669   * Miscellaneous configurable options
670   */
671  #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
672  
673  /*
674   * For booting Linux, the board info and command line data
675   * have to be in the first 64 MB of memory, since this is
676   * the maximum mapped by the Linux kernel during initialization.
677   */
678  #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
679  #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
680  
681  #ifdef CONFIG_CMD_KGDB
682  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
683  #endif
684  
685  /*
686   * Environment Configuration
687   */
688  #define CONFIG_ROOTPATH		"/opt/nfsroot"
689  #define CONFIG_BOOTFILE		"uImage"
690  #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
691  
692  /* default location for tftp and bootm */
693  #define CONFIG_LOADADDR		1000000
694  
695  #define __USB_PHY_TYPE	ulpi
696  
697  #ifdef CONFIG_ARCH_B4860
698  #define HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,"	\
699  			"bank_intlv=cs0_cs1;"	\
700  			"en_cpc:cpc2;"
701  #else
702  #define	HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
703  #endif
704  
705  #define	CONFIG_EXTRA_ENV_SETTINGS				\
706  	HWCONFIG						\
707  	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
708  	"netdev=eth0\0"						\
709  	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
710  	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
711  	"tftpflash=tftpboot $loadaddr $uboot && "		\
712  	"protect off $ubootaddr +$filesize && "			\
713  	"erase $ubootaddr +$filesize && "			\
714  	"cp.b $loadaddr $ubootaddr $filesize && "		\
715  	"protect on $ubootaddr +$filesize && "			\
716  	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
717  	"consoledev=ttyS0\0"					\
718  	"ramdiskaddr=2000000\0"					\
719  	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
720  	"fdtaddr=1e00000\0"					\
721  	"fdtfile=b4860qds/b4860qds.dtb\0"				\
722  	"bdev=sda3\0"
723  
724  /* For emulation this causes u-boot to jump to the start of the proof point
725     app code automatically */
726  #define CONFIG_PROOF_POINTS			\
727   "setenv bootargs root=/dev/$bdev rw "		\
728   "console=$consoledev,$baudrate $othbootargs;"	\
729   "cpu 1 release 0x29000000 - - -;"		\
730   "cpu 2 release 0x29000000 - - -;"		\
731   "cpu 3 release 0x29000000 - - -;"		\
732   "cpu 4 release 0x29000000 - - -;"		\
733   "cpu 5 release 0x29000000 - - -;"		\
734   "cpu 6 release 0x29000000 - - -;"		\
735   "cpu 7 release 0x29000000 - - -;"		\
736   "go 0x29000000"
737  
738  #define CONFIG_HVBOOT	\
739   "setenv bootargs config-addr=0x60000000; "	\
740   "bootm 0x01000000 - 0x00f00000"
741  
742  #define CONFIG_ALU				\
743   "setenv bootargs root=/dev/$bdev rw "		\
744   "console=$consoledev,$baudrate $othbootargs;"	\
745   "cpu 1 release 0x01000000 - - -;"		\
746   "cpu 2 release 0x01000000 - - -;"		\
747   "cpu 3 release 0x01000000 - - -;"		\
748   "cpu 4 release 0x01000000 - - -;"		\
749   "cpu 5 release 0x01000000 - - -;"		\
750   "cpu 6 release 0x01000000 - - -;"		\
751   "cpu 7 release 0x01000000 - - -;"		\
752   "go 0x01000000"
753  
754  #define CONFIG_LINUX				\
755   "setenv bootargs root=/dev/ram rw "		\
756   "console=$consoledev,$baudrate $othbootargs;"	\
757   "setenv ramdiskaddr 0x02000000;"		\
758   "setenv fdtaddr 0x01e00000;"			\
759   "setenv loadaddr 0x1000000;"			\
760   "bootm $loadaddr $ramdiskaddr $fdtaddr"
761  
762  #define CONFIG_HDBOOT					\
763  	"setenv bootargs root=/dev/$bdev rw "		\
764  	"console=$consoledev,$baudrate $othbootargs;"	\
765  	"tftp $loadaddr $bootfile;"			\
766  	"tftp $fdtaddr $fdtfile;"			\
767  	"bootm $loadaddr - $fdtaddr"
768  
769  #define CONFIG_NFSBOOTCOMMAND			\
770  	"setenv bootargs root=/dev/nfs rw "	\
771  	"nfsroot=$serverip:$rootpath "		\
772  	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
773  	"console=$consoledev,$baudrate $othbootargs;"	\
774  	"tftp $loadaddr $bootfile;"		\
775  	"tftp $fdtaddr $fdtfile;"		\
776  	"bootm $loadaddr - $fdtaddr"
777  
778  #define CONFIG_RAMBOOTCOMMAND				\
779  	"setenv bootargs root=/dev/ram rw "		\
780  	"console=$consoledev,$baudrate $othbootargs;"	\
781  	"tftp $ramdiskaddr $ramdiskfile;"		\
782  	"tftp $loadaddr $bootfile;"			\
783  	"tftp $fdtaddr $fdtfile;"			\
784  	"bootm $loadaddr $ramdiskaddr $fdtaddr"
785  
786  #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
787  
788  #include <asm/fsl_secure_boot.h>
789  
790  #endif	/* __CONFIG_H */
791