1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #ifndef COMMON_TIMING_PARAMS_H
8 #define COMMON_TIMING_PARAMS_H
9 
10 typedef struct {
11 	/* parameters to constrict */
12 
13 	unsigned int tckmin_x_ps;
14 	unsigned int tckmax_ps;
15 	unsigned int trcd_ps;
16 	unsigned int trp_ps;
17 	unsigned int tras_ps;
18 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
19 	unsigned int taamin_ps;
20 #endif
21 
22 #ifdef CONFIG_SYS_FSL_DDR4
23 	unsigned int trfc1_ps;
24 	unsigned int trfc2_ps;
25 	unsigned int trfc4_ps;
26 	unsigned int trrds_ps;
27 	unsigned int trrdl_ps;
28 	unsigned int tccdl_ps;
29 	unsigned int trfc_slr_ps;
30 #else
31 	unsigned int twtr_ps;	/* maximum = 63750 ps */
32 	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
33 					   = 511750 ps */
34 
35 	unsigned int trrd_ps;	/* maximum = 63750 ps */
36 	unsigned int trtp_ps;	/* byte 38, spd->trtp */
37 #endif
38 	unsigned int twr_ps;	/* maximum = 63750 ps */
39 	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
40 
41 	unsigned int refresh_rate_ps;
42 	unsigned int extended_op_srt;
43 
44 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
45 	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
46 	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
47 	unsigned int tds_ps;	/* byte 34, spd->data_setup */
48 	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
49 	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
50 	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
51 #endif
52 
53 	unsigned int ndimms_present;
54 	unsigned int lowest_common_spd_caslat;
55 	unsigned int highest_common_derated_caslat;
56 	unsigned int additive_latency;
57 	unsigned int all_dimms_burst_lengths_bitmask;
58 	unsigned int all_dimms_registered;
59 	unsigned int all_dimms_unbuffered;
60 	unsigned int all_dimms_ecc_capable;
61 
62 	unsigned long long total_mem;
63 	unsigned long long base_address;
64 
65 	/* DDR3 RDIMM */
66 	unsigned char rcw[16];	/* Register Control Word 0-15 */
67 } common_timing_params_t;
68 
69 #endif
70