1 /* $Id$ */ 2 3 #ifndef _REGS_H 4 #define _REGS_H 5 6 /* Special Purpose Registers */ 7 8 #define SPR_CR -1 9 #define SPR_MSR -2 10 11 #define SPR_XER 1 12 #define SPR_LR 8 13 #define SPR_CTR 9 14 #define SPR_DSISR 18 15 #define SPR_DAR 19 16 #define SPR_DEC 22 17 #define SPR_SRR0 26 18 #define SPR_SRR1 27 19 #define SPR_EIE 80 20 #define SPR_EID 81 21 #define SPR_CMPA 144 22 #define SPR_CMPB 145 23 #define SPR_CMPC 146 24 #define SPR_CMPD 147 25 #define SPR_ICR 148 26 #define SPR_DER 149 27 #define SPR_COUNTA 150 28 #define SPR_COUNTB 151 29 #define SPR_CMPE 152 30 #define SPR_CMPF 153 31 #define SPR_CMPG 154 32 #define SPR_CMPH 155 33 #define SPR_LCTRL1 156 34 #define SPR_LCTRL2 157 35 #define SPR_ICTRL 158 36 #define SPR_BAR 159 37 #define SPR_USPRG0 256 38 #define SPR_SPRG4_RO 260 39 #define SPR_SPRG5_RO 261 40 #define SPR_SPRG6_RO 262 41 #define SPR_SPRG7_RO 263 42 #define SPR_SPRG0 272 43 #define SPR_SPRG1 273 44 #define SPR_SPRG2 274 45 #define SPR_SPRG3 275 46 #define SPR_SPRG4 276 47 #define SPR_SPRG5 277 48 #define SPR_SPRG6 278 49 #define SPR_SPRG7 279 50 #define SPR_EAR 282 /* MPC603e core */ 51 #define SPR_TBL 284 52 #define SPR_TBU 285 53 #define SPR_PVR 287 54 #define SPR_IC_CST 560 55 #define SPR_IC_ADR 561 56 #define SPR_IC_DAT 562 57 #define SPR_DC_CST 568 58 #define SPR_DC_ADR 569 59 #define SPR_DC_DAT 570 60 #define SPR_DPDR 630 61 #define SPR_IMMR 638 62 #define SPR_MI_CTR 784 63 #define SPR_MI_AP 786 64 #define SPR_MI_EPN 787 65 #define SPR_MI_TWC 789 66 #define SPR_MI_RPN 790 67 #define SPR_MD_CTR 792 68 #define SPR_M_CASID 793 69 #define SPR_MD_AP 794 70 #define SPR_MD_EPN 795 71 #define SPR_M_TWB 796 72 #define SPR_MD_TWC 797 73 #define SPR_MD_RPN 798 74 #define SPR_M_TW 799 75 #define SPR_MI_DBCAM 816 76 #define SPR_MI_DBRAM0 817 77 #define SPR_MI_DBRAM1 818 78 #define SPR_MD_DBCAM 824 79 #define SPR_MD_DBRAM0 825 80 #define SPR_MD_DBRAM1 826 81 #define SPR_ZPR 944 82 #define SPR_PID 945 83 #define SPR_CCR0 947 84 #define SPR_IAC3 948 85 #define SPR_IAC4 949 86 #define SPR_DVC1 950 87 #define SPR_DVC2 951 88 #define SPR_SGR 953 89 #define SPR_DCWR 954 90 #define SPR_SLER 955 91 #define SPR_SU0R 956 92 #define SPR_DBCR1 957 93 #define SPR_ICDBDR 979 94 #define SPR_ESR 980 95 #define SPR_DEAR 981 96 #define SPR_EVPR 982 97 #define SPR_TSR 984 98 #define SPR_TCR 986 99 #define SPR_PIT 987 100 #define SPR_SRR2 990 101 #define SPR_SRR3 991 102 #define SPR_DBSR 1008 103 #define SPR_DBCR0 1010 104 #define SPR_IABR 1010 /* MPC603e core */ 105 #define SPR_IAC1 1012 106 #define SPR_IAC2 1013 107 #define SPR_DAC1 1014 108 #define SPR_DAC2 1015 109 #define SPR_DCCR 1018 110 #define SPR_ICCR 1019 111 112 /* Bits for the DBCR0 register */ 113 #define DBCR0_EDM 0x80000000 114 #define DBCR0_IDM 0x40000000 115 #define DBCR0_RST 0x30000000 116 #define DBCR0_IC 0x08000000 117 #define DBCR0_BT 0x04000000 118 #define DBCR0_EDE 0x02000000 119 #define DBCR0_TDE 0x01000000 120 #define DBCR0_IA1 0x00800000 121 #define DBCR0_IA2 0x00400000 122 #define DBCR0_IA12 0x00200000 123 #define DBCR0_IA12X 0x00100000 124 #define DBCR0_IA3 0x00080000 125 #define DBCR0_IA4 0x00040000 126 #define DBCR0_IA34 0x00020000 127 #define DBCR0_IA34X 0x00010000 128 #define DBCR0_IA12T 0x00008000 129 #define DBCR0_IA34T 0x00004000 130 #define DBCR0_FT 0x00000001 131 132 /* Bits for the DBCR1 register */ 133 #define DBCR1_D1R 0x80000000 134 #define DBCR1_D2R 0x40000000 135 #define DBCR1_D1W 0x20000000 136 #define DBCR1_D2W 0x10000000 137 #define DBCR1_D1S 0x0C000000 138 #define DBCR1_D2S 0x03000000 139 #define DBCR1_DA12 0x00800000 140 #define DBCR1_DA12X 0x00400000 141 #define DBCR1_DV1M 0x000C0000 142 #define DBCR1_DV2M 0x00030000 143 #define DBCR1_DV1BE 0x0000F000 144 #define DBCR1_DV2BE 0x00000F00 145 146 /* 147 * DBSR bits which have conflicting definitions on true Book E versus PPC40x 148 */ 149 #ifdef CONFIG_BOOKE 150 #define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ 151 #define DBSR_IA2 0x00400000 /* Instr Address Compare 2 Event */ 152 #define DBSR_IA3 0x00200000 /* Instr Address Compare 3 Event */ 153 #define DBSR_IA4 0x00100000 /* Instr Address Compare 4 Event */ 154 #endif 155 #ifndef CONFIG_440 156 #define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ 157 #define DBSR_IA2 0x02000000 /* Instr Address Compare 2 Event */ 158 #define DBSR_IA3 0x00080000 /* Instr Address Compare 3 Event */ 159 #define DBSR_IA4 0x00040000 /* Instr Address Compare 4 Event */ 160 #endif 161 162 struct spr_info { 163 int spr_val; 164 char spr_name[ 10 ]; 165 }; 166 167 extern struct spr_info spr_map[]; 168 extern const unsigned int n_sprs; 169 170 171 #define SET_REGISTER( str, val ) \ 172 ({ unsigned long __value = (val); \ 173 asm volatile( str : : "r" (__value)); \ 174 __value; }) 175 176 #define GET_REGISTER( str ) \ 177 ({ unsigned long __value; \ 178 asm volatile( str : "=r" (__value) : ); \ 179 __value; }) 180 181 #define GET_CR() GET_REGISTER( "mfcr %0" ) 182 #define SET_CR(val) SET_REGISTER( "mtcr %0", val ) 183 #define GET_MSR() GET_REGISTER( "mfmsr %0" ) 184 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) 185 #define GET_XER() GET_REGISTER( "mfspr %0,1" ) 186 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) 187 #define GET_LR() GET_REGISTER( "mfspr %0,8" ) 188 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) 189 #define GET_CTR() GET_REGISTER( "mfspr %0,9" ) 190 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) 191 #define GET_DSISR() GET_REGISTER( "mfspr %0,18" ) 192 #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) 193 #define GET_DAR() GET_REGISTER( "mfspr %0,19" ) 194 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) 195 #define GET_DEC() GET_REGISTER( "mfspr %0,22" ) 196 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) 197 #define GET_SRR0() GET_REGISTER( "mfspr %0,26" ) 198 #define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val ) 199 #define GET_SRR1() GET_REGISTER( "mfspr %0,27" ) 200 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val ) 201 #define GET_EIE() GET_REGISTER( "mfspr %0,80" ) 202 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val ) 203 #define GET_EID() GET_REGISTER( "mfspr %0,81" ) 204 #define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val ) 205 #define GET_CMPA() GET_REGISTER( "mfspr %0,144" ) 206 #define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val ) 207 #define GET_CMPB() GET_REGISTER( "mfspr %0,145" ) 208 #define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val ) 209 #define GET_CMPC() GET_REGISTER( "mfspr %0,146" ) 210 #define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val ) 211 #define GET_CMPD() GET_REGISTER( "mfspr %0,147" ) 212 #define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val ) 213 #define GET_ICR() GET_REGISTER( "mfspr %0,148" ) 214 #define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val ) 215 #define GET_DER() GET_REGISTER( "mfspr %0,149" ) 216 #define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val ) 217 #define GET_COUNTA() GET_REGISTER( "mfspr %0,150" ) 218 #define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val ) 219 #define GET_COUNTB() GET_REGISTER( "mfspr %0,151" ) 220 #define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val ) 221 #define GET_CMPE() GET_REGISTER( "mfspr %0,152" ) 222 #define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val ) 223 #define GET_CMPF() GET_REGISTER( "mfspr %0,153" ) 224 #define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val ) 225 #define GET_CMPG() GET_REGISTER( "mfspr %0,154" ) 226 #define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val ) 227 #define GET_CMPH() GET_REGISTER( "mfspr %0,155" ) 228 #define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val ) 229 #define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" ) 230 #define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val ) 231 #define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" ) 232 #define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val ) 233 #define GET_ICTRL() GET_REGISTER( "mfspr %0,158" ) 234 #define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val ) 235 #define GET_BAR() GET_REGISTER( "mfspr %0,159" ) 236 #define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val ) 237 #define GET_USPRG0() GET_REGISTER( "mfspr %0,256" ) 238 #define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val ) 239 #define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" ) 240 #define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val ) 241 #define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" ) 242 #define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val ) 243 #define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" ) 244 #define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val ) 245 #define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" ) 246 #define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val ) 247 #define GET_SPRG0() GET_REGISTER( "mfspr %0,272" ) 248 #define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val ) 249 #define GET_SPRG1() GET_REGISTER( "mfspr %0,273" ) 250 #define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val ) 251 #define GET_SPRG2() GET_REGISTER( "mfspr %0,274" ) 252 #define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val ) 253 #define GET_SPRG3() GET_REGISTER( "mfspr %0,275" ) 254 #define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val ) 255 #define GET_SPRG4() GET_REGISTER( "mfspr %0,276" ) 256 #define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val ) 257 #define GET_SPRG5() GET_REGISTER( "mfspr %0,277" ) 258 #define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val ) 259 #define GET_SPRG6() GET_REGISTER( "mfspr %0,278" ) 260 #define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val ) 261 #define GET_SPRG7() GET_REGISTER( "mfspr %0,279" ) 262 #define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val ) 263 #define GET_EAR() GET_REGISTER( "mfspr %0,282" ) 264 #define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val ) 265 #define GET_TBL() GET_REGISTER( "mfspr %0,284" ) 266 #define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val ) 267 #define GET_TBU() GET_REGISTER( "mfspr %0,285" ) 268 #define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val ) 269 #define GET_PVR() GET_REGISTER( "mfspr %0,287" ) 270 #define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val ) 271 #define GET_IC_CST() GET_REGISTER( "mfspr %0,560" ) 272 #define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val ) 273 #define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" ) 274 #define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val ) 275 #define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" ) 276 #define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val ) 277 #define GET_DC_CST() GET_REGISTER( "mfspr %0,568" ) 278 #define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val ) 279 #define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" ) 280 #define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val ) 281 #define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" ) 282 #define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val ) 283 #define GET_DPDR() GET_REGISTER( "mfspr %0,630" ) 284 #define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val ) 285 #define GET_IMMR() GET_REGISTER( "mfspr %0,638" ) 286 #define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val ) 287 #define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" ) 288 #define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val ) 289 #define GET_MI_AP() GET_REGISTER( "mfspr %0,786" ) 290 #define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val ) 291 #define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" ) 292 #define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val ) 293 #define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" ) 294 #define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val ) 295 #define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" ) 296 #define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val ) 297 #define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" ) 298 #define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val ) 299 #define GET_M_CASID() GET_REGISTER( "mfspr %0,793" ) 300 #define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val ) 301 #define GET_MD_AP() GET_REGISTER( "mfspr %0,794" ) 302 #define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val ) 303 #define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" ) 304 #define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val ) 305 #define GET_M_TWB() GET_REGISTER( "mfspr %0,796" ) 306 #define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val ) 307 #define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" ) 308 #define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val ) 309 #define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" ) 310 #define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val ) 311 #define GET_M_TW() GET_REGISTER( "mfspr %0,799" ) 312 #define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val ) 313 #define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" ) 314 #define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val ) 315 #define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" ) 316 #define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val ) 317 #define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" ) 318 #define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val ) 319 #define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" ) 320 #define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val ) 321 #define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" ) 322 #define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val ) 323 #define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" ) 324 #define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val ) 325 #define GET_ZPR() GET_REGISTER( "mfspr %0,944" ) 326 #define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val ) 327 #define GET_PID() GET_REGISTER( "mfspr %0,945" ) 328 #define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val ) 329 #define GET_CCR0() GET_REGISTER( "mfspr %0,947" ) 330 #define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val ) 331 #define GET_IAC3() GET_REGISTER( "mfspr %0,948" ) 332 #define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val ) 333 #define GET_IAC4() GET_REGISTER( "mfspr %0,949" ) 334 #define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val ) 335 #define GET_DVC1() GET_REGISTER( "mfspr %0,950" ) 336 #define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val ) 337 #define GET_DVC2() GET_REGISTER( "mfspr %0,951" ) 338 #define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val ) 339 #define GET_SGR() GET_REGISTER( "mfspr %0,953" ) 340 #define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val ) 341 #define GET_DCWR() GET_REGISTER( "mfspr %0,954" ) 342 #define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val ) 343 #define GET_SLER() GET_REGISTER( "mfspr %0,955" ) 344 #define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val ) 345 #define GET_SU0R() GET_REGISTER( "mfspr %0,956" ) 346 #define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val ) 347 #define GET_DBCR1() GET_REGISTER( "mfspr %0,957" ) 348 #define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val ) 349 #define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" ) 350 #define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val ) 351 #define GET_ESR() GET_REGISTER( "mfspr %0,980" ) 352 #define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val ) 353 #define GET_DEAR() GET_REGISTER( "mfspr %0,981" ) 354 #define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val ) 355 #define GET_EVPR() GET_REGISTER( "mfspr %0,982" ) 356 #define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val ) 357 #define GET_TSR() GET_REGISTER( "mfspr %0,984" ) 358 #define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val ) 359 #define GET_TCR() GET_REGISTER( "mfspr %0,986" ) 360 #define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val ) 361 #define GET_PIT() GET_REGISTER( "mfspr %0,987" ) 362 #define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val ) 363 #define GET_SRR2() GET_REGISTER( "mfspr %0,990" ) 364 #define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val ) 365 #define GET_SRR3() GET_REGISTER( "mfspr %0,991" ) 366 #define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val ) 367 #define GET_DBSR() GET_REGISTER( "mfspr %0,1008" ) 368 #define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val ) 369 #define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" ) 370 #define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val ) 371 #define GET_IABR() GET_REGISTER( "mfspr %0,1010" ) 372 #define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val ) 373 #define GET_IAC1() GET_REGISTER( "mfspr %0,1012" ) 374 #define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val ) 375 #define GET_IAC2() GET_REGISTER( "mfspr %0,1013" ) 376 #define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val ) 377 #define GET_DAC1() GET_REGISTER( "mfspr %0,1014" ) 378 #define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val ) 379 #define GET_DAC2() GET_REGISTER( "mfspr %0,1015" ) 380 #define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val ) 381 #define GET_DCCR() GET_REGISTER( "mfspr %0,1018" ) 382 #define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val ) 383 #define GET_ICCR() GET_REGISTER( "mfspr %0,1019" ) 384 #define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val ) 385 386 #endif /* _REGS_H */ 387 388 389 /* 390 * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks 391 * All rights reserved. 392 * 393 * Redistribution and use in source and binary forms are freely 394 * permitted provided that the above copyright notice and this 395 * paragraph and the following disclaimer are duplicated in all 396 * such forms. 397 * 398 * This software is provided "AS IS" and without any express or 399 * implied warranties, including, without limitation, the implied 400 * warranties of merchantability and fitness for a particular 401 * purpose. 402 */ 403