1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2baaa7dd7SNikita Kiryanov /* 3baaa7dd7SNikita Kiryanov * atmel_lcd.h - Atmel LCD Controller structures 4baaa7dd7SNikita Kiryanov * 5baaa7dd7SNikita Kiryanov * (C) Copyright 2001 6baaa7dd7SNikita Kiryanov * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7baaa7dd7SNikita Kiryanov */ 8baaa7dd7SNikita Kiryanov 9baaa7dd7SNikita Kiryanov #ifndef _ATMEL_LCD_H_ 10baaa7dd7SNikita Kiryanov #define _ATMEL_LCD_H_ 11baaa7dd7SNikita Kiryanov 129dc89a05SSimon Glass /** 139dc89a05SSimon Glass * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model 149dc89a05SSimon Glass * 159dc89a05SSimon Glass * @timing_index: Index of LCD timing to use in device tree node 169dc89a05SSimon Glass */ 179dc89a05SSimon Glass struct atmel_lcd_platdata { 189dc89a05SSimon Glass int timing_index; 199dc89a05SSimon Glass }; 209dc89a05SSimon Glass 21baaa7dd7SNikita Kiryanov typedef struct vidinfo { 22baaa7dd7SNikita Kiryanov ushort vl_col; /* Number of columns (i.e. 640) */ 23baaa7dd7SNikita Kiryanov ushort vl_row; /* Number of rows (i.e. 480) */ 24604c7d4aSHannes Petermaier ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ 25baaa7dd7SNikita Kiryanov u_long vl_clk; /* pixel clock in ps */ 26baaa7dd7SNikita Kiryanov 27baaa7dd7SNikita Kiryanov /* LCD configuration register */ 28baaa7dd7SNikita Kiryanov u_long vl_sync; /* Horizontal / vertical sync */ 29baaa7dd7SNikita Kiryanov u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 30baaa7dd7SNikita Kiryanov u_long vl_tft; /* 0 = passive, 1 = TFT */ 31baaa7dd7SNikita Kiryanov u_long vl_cont_pol_low; /* contrast polarity is low */ 32baaa7dd7SNikita Kiryanov u_long vl_clk_pol; /* clock polarity */ 33baaa7dd7SNikita Kiryanov 34baaa7dd7SNikita Kiryanov /* Horizontal control register. */ 35baaa7dd7SNikita Kiryanov u_long vl_hsync_len; /* Length of horizontal sync */ 36baaa7dd7SNikita Kiryanov u_long vl_left_margin; /* Time from sync to picture */ 37baaa7dd7SNikita Kiryanov u_long vl_right_margin; /* Time from picture to sync */ 38baaa7dd7SNikita Kiryanov 39baaa7dd7SNikita Kiryanov /* Vertical control register. */ 40baaa7dd7SNikita Kiryanov u_long vl_vsync_len; /* Length of vertical sync */ 41baaa7dd7SNikita Kiryanov u_long vl_upper_margin; /* Time from sync to picture */ 42baaa7dd7SNikita Kiryanov u_long vl_lower_margin; /* Time from picture to sync */ 43baaa7dd7SNikita Kiryanov 44baaa7dd7SNikita Kiryanov u_long mmio; /* Memory mapped registers */ 45d330e04dSWenyou Yang 46d330e04dSWenyou Yang u_int logo_width; 47d330e04dSWenyou Yang u_int logo_height; 48d330e04dSWenyou Yang int logo_x_offset; 49d330e04dSWenyou Yang int logo_y_offset; 50d330e04dSWenyou Yang u_long logo_addr; 51baaa7dd7SNikita Kiryanov } vidinfo_t; 52baaa7dd7SNikita Kiryanov 53d330e04dSWenyou Yang void atmel_logo_info(vidinfo_t *info); 54d330e04dSWenyou Yang void microchip_logo_info(vidinfo_t *info); 55d330e04dSWenyou Yang 56baaa7dd7SNikita Kiryanov #endif 57