xref: /openbmc/u-boot/include/atmel_hlcdc.h (revision 9d466f2f)
1 /*
2  *  Header file for AT91/AT32 MULTI LAYER LCD Controller
3  *
4  *  Data structure and register user interface
5  *
6  *  Copyright (C) 2012 Atmel Corporation
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 #ifndef __ATMEL_HLCDC_H__
11 #define __ATMEL_HLCDC_H__
12 
13 /* Atmel multi layer lcdc hardware registers */
14 struct atmel_hlcd_regs {
15 	u32	lcdc_lcdcfg0;
16 	u32	lcdc_lcdcfg1;
17 	u32	lcdc_lcdcfg2;
18 	u32	lcdc_lcdcfg3;
19 	u32	lcdc_lcdcfg4;
20 	u32	lcdc_lcdcfg5;
21 	u32	lcdc_lcdcfg6;
22 	u32	res1;
23 	u32	lcdc_lcden;
24 	u32	lcdc_lcddis;
25 	u32	lcdc_lcdsr;
26 	u32	res2;
27 	u32	lcdc_lcdidr;
28 	u32	res3[3];
29 	u32	lcdc_basecher;
30 	u32	res4[3];
31 	u32	lcdc_baseidr;
32 	u32	res5[3];
33 	u32	lcdc_baseaddr;
34 	u32	lcdc_basectrl;
35 	u32	lcdc_basenext;
36 	u32	lcdc_basecfg0;
37 	u32	lcdc_basecfg1;
38 	u32	lcdc_basecfg2;
39 	u32	lcdc_basecfg3;
40 	u32	lcdc_basecfg4;
41 };
42 
43 #define LCDC_LCDCFG0_CLKPOL	(0x1 << 0)
44 #define LCDC_LCDCFG0_CLKSEL	(0x1 << 2)
45 #define LCDC_LCDCFG0_CLKPWMSEL	(0x1 << 3)
46 #define LCDC_LCDCFG0_CGDISBASE	(0x1 << 8)
47 #define LCDC_LCDCFG0_CGDISOVR1	(0x1 << 9)
48 #define LCDC_LCDCFG0_CGDISHEO	(0x1 << 11)
49 #define LCDC_LCDCFG0_CGDISHCR	(0x1 << 12)
50 #define LCDC_LCDCFG0_CLKDIV_Pos	16
51 #define LCDC_LCDCFG0_CLKDIV_Msk	(0xff << LCDC_LCDCFG0_CLKDIV_Pos)
52 #define LCDC_LCDCFG0_CLKDIV(value) \
53 	((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
54 
55 #define LCDC_LCDCFG1_HSPW_Pos	0
56 #define LCDC_LCDCFG1_HSPW_Msk	(0x3f << LCDC_LCDCFG1_HSPW_Pos)
57 #define LCDC_LCDCFG1_HSPW(value) \
58 	((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
59 #define LCDC_LCDCFG1_VSPW_Pos	16
60 #define LCDC_LCDCFG1_VSPW_Msk	(0x3f << LCDC_LCDCFG1_VSPW_Pos)
61 #define LCDC_LCDCFG1_VSPW(value) \
62 	((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
63 
64 #define LCDC_LCDCFG2_VFPW_Pos	0
65 #define LCDC_LCDCFG2_VFPW_Msk	(0x3f << LCDC_LCDCFG2_VFPW_Pos)
66 #define LCDC_LCDCFG2_VFPW(value) \
67 	((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
68 #define LCDC_LCDCFG2_VBPW_Pos	16
69 #define LCDC_LCDCFG2_VBPW_Msk	(0x3f << LCDC_LCDCFG2_VBPW_Pos)
70 #define LCDC_LCDCFG2_VBPW(value) \
71 	((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
72 
73 #define LCDC_LCDCFG3_HFPW_Pos	0
74 #define LCDC_LCDCFG3_HFPW_Msk	(0xff << LCDC_LCDCFG3_HFPW_Pos)
75 #define LCDC_LCDCFG3_HFPW(value) \
76 	((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
77 #define LCDC_LCDCFG3_HBPW_Pos	16
78 #define LCDC_LCDCFG3_HBPW_Msk	(0xff << LCDC_LCDCFG3_HBPW_Pos)
79 #define LCDC_LCDCFG3_HBPW(value) \
80 	((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
81 
82 #define LCDC_LCDCFG4_PPL_Pos	0
83 #define LCDC_LCDCFG4_PPL_Msk	(0x7ff << LCDC_LCDCFG4_PPL_Pos)
84 #define LCDC_LCDCFG4_PPL(value) \
85 	((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
86 #define LCDC_LCDCFG4_RPF_Pos	16
87 #define LCDC_LCDCFG4_RPF_Msk	(0x7ff << LCDC_LCDCFG4_RPF_Pos)
88 #define LCDC_LCDCFG4_RPF(value) \
89 	((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
90 
91 #define LCDC_LCDCFG5_HSPOL	(0x1 << 0)
92 #define LCDC_LCDCFG5_VSPOL	(0x1 << 1)
93 #define LCDC_LCDCFG5_VSPDLYS	(0x1 << 2)
94 #define LCDC_LCDCFG5_VSPDLYE	(0x1 << 3)
95 #define LCDC_LCDCFG5_DISPPOL	(0x1 << 4)
96 #define LCDC_LCDCFG5_SERIAL	(0x1 << 5)
97 #define LCDC_LCDCFG5_DITHER	(0x1 << 6)
98 #define LCDC_LCDCFG5_DISPDLY	(0x1 << 7)
99 #define LCDC_LCDCFG5_MODE_Pos	8
100 #define LCDC_LCDCFG5_MODE_Msk	(0x3 << LCDC_LCDCFG5_MODE_Pos)
101 #define LCDC_LCDCFG5_MODE_OUTPUT_12BPP	(0x0 << 8)
102 #define LCDC_LCDCFG5_MODE_OUTPUT_16BPP	(0x1 << 8)
103 #define LCDC_LCDCFG5_MODE_OUTPUT_18BPP	(0x2 << 8)
104 #define LCDC_LCDCFG5_MODE_OUTPUT_24BPP	(0x3 << 8)
105 #define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
106 #define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
107 #define LCDC_LCDCFG5_GUARDTIME_Pos	16
108 #define LCDC_LCDCFG5_GUARDTIME_Msk	(0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
109 #define LCDC_LCDCFG5_GUARDTIME(value) \
110 	((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
111 
112 #define LCDC_LCDCFG6_PWMPS_Pos		0
113 #define LCDC_LCDCFG6_PWMPS_Msk		(0x7 << LCDC_LCDCFG6_PWMPS_Pos)
114 #define LCDC_LCDCFG6_PWMPS(value) \
115 	((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
116 #define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
117 #define LCDC_LCDCFG6_PWMCVAL_Pos	8
118 #define LCDC_LCDCFG6_PWMCVAL_Msk	(0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
119 #define LCDC_LCDCFG6_PWMCVAL(value) \
120 	((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
121 
122 #define LCDC_LCDEN_CLKEN	(0x1 << 0)
123 #define LCDC_LCDEN_SYNCEN	(0x1 << 1)
124 #define LCDC_LCDEN_DISPEN	(0x1 << 2)
125 #define LCDC_LCDEN_PWMEN	(0x1 << 3)
126 
127 #define LCDC_LCDDIS_CLKDIS	(0x1 << 0)
128 #define LCDC_LCDDIS_SYNCDIS	(0x1 << 1)
129 #define LCDC_LCDDIS_DISPDIS	(0x1 << 2)
130 #define LCDC_LCDDIS_PWMDIS	(0x1 << 3)
131 #define LCDC_LCDDIS_CLKRST	(0x1 << 8)
132 #define LCDC_LCDDIS_SYNCRST	(0x1 << 9)
133 #define LCDC_LCDDIS_DISPRST	(0x1 << 10)
134 #define LCDC_LCDDIS_PWMRST	(0x1 << 11)
135 
136 #define LCDC_LCDSR_CLKSTS	(0x1 << 0)
137 #define LCDC_LCDSR_LCDSTS	(0x1 << 1)
138 #define LCDC_LCDSR_DISPSTS	(0x1 << 2)
139 #define LCDC_LCDSR_PWMSTS	(0x1 << 3)
140 #define LCDC_LCDSR_SIPSTS	(0x1 << 4)
141 
142 #define LCDC_LCDIDR_SOFID	(0x1 << 0)
143 #define LCDC_LCDIDR_DISID	(0x1 << 1)
144 #define LCDC_LCDIDR_DISPID	(0x1 << 2)
145 #define LCDC_LCDIDR_FIFOERRID	(0x1 << 4)
146 #define LCDC_LCDIDR_BASEID	(0x1 << 8)
147 #define LCDC_LCDIDR_OVR1ID	(0x1 << 9)
148 #define LCDC_LCDIDR_HEOID	(0x1 << 11)
149 #define LCDC_LCDIDR_HCRID	(0x1 << 12)
150 
151 #define LCDC_BASECHER_CHEN	(0x1 << 0)
152 #define LCDC_BASECHER_UPDATEEN	(0x1 << 1)
153 #define LCDC_BASECHER_A2QEN	(0x1 << 2)
154 
155 #define LCDC_BASEIDR_DMA	(0x1 << 2)
156 #define LCDC_BASEIDR_DSCR	(0x1 << 3)
157 #define LCDC_BASEIDR_ADD	(0x1 << 4)
158 #define LCDC_BASEIDR_DONE	(0x1 << 5)
159 #define LCDC_BASEIDR_OVR	(0x1 << 6)
160 
161 #define LCDC_BASECTRL_DFETCH	(0x1 << 0)
162 #define LCDC_BASECTRL_LFETCH	(0x1 << 1)
163 #define LCDC_BASECTRL_DMAIEN	(0x1 << 2)
164 #define LCDC_BASECTRL_DSCRIEN	(0x1 << 3)
165 #define LCDC_BASECTRL_ADDIEN	(0x1 << 4)
166 #define LCDC_BASECTRL_DONEIEN	(0x1 << 5)
167 
168 #define LCDC_BASECFG0_BLEN_Pos		4
169 #define LCDC_BASECFG0_BLEN_AHB_SINGLE	(0x0 << 4)
170 #define LCDC_BASECFG0_BLEN_AHB_INCR4	(0x1 << 4)
171 #define LCDC_BASECFG0_BLEN_AHB_INCR8	(0x2 << 4)
172 #define LCDC_BASECFG0_BLEN_AHB_INCR16	(0x3 << 4)
173 #define LCDC_BASECFG0_DLBO		(0x1 << 8)
174 
175 #define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444		(0x0 << 4)
176 #define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444		(0x1 << 4)
177 #define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444		(0x2 << 4)
178 #define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565		(0x3 << 4)
179 #define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555		(0x4 << 4)
180 #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666		(0x5 << 4)
181 #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
182 #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666		(0x7 << 4)
183 #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED		(0x8 << 4)
184 #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888		(0x9 << 4)
185 #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
186 #define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888		(0xB << 4)
187 #define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888		(0xC << 4)
188 #define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888		(0xD << 4)
189 
190 #define LCDC_BASECFG2_XSTRIDE_Pos 0
191 #define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
192 #define LCDC_BASECFG2_XSTRIDE(value) \
193 	((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
194 
195 #define LCDC_BASECFG3_BDEF_Pos	0
196 #define LCDC_BASECFG3_BDEF_Msk	(0xff << LCDC_BASECFG3_BDEF_Pos)
197 #define LCDC_BASECFG3_BDEF(value) \
198 	((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
199 #define LCDC_BASECFG3_GDEF_Pos	8
200 #define LCDC_BASECFG3_GDEF_Msk	(0xff << LCDC_BASECFG3_GDEF_Pos)
201 #define LCDC_BASECFG3_GDEF(value) \
202 	((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
203 #define LCDC_BASECFG3_RDEF_Pos	16
204 #define LCDC_BASECFG3_RDEF_Msk	(0xff << LCDC_BASECFG3_RDEF_Pos)
205 #define LCDC_BASECFG3_RDEF(value) \
206 	((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
207 
208 #define LCDC_BASECLUT_BCLUT_Pos 0
209 #define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
210 #define LCDC_BASECLUT_GCLUT_Pos 8
211 #define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
212 #define LCDC_BASECLUT_RCLUT_Pos 16
213 #define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
214 
215 #define LCDC_BASECFG4_DMA	(0x1 << 8)
216 #define LCDC_BASECFG4_REP	(0x1 << 9)
217 
218 struct lcd_dma_desc {
219 	u32	address;
220 	u32	control;
221 	u32	next;
222 };
223 
224 #define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
225 
226 #endif /* __ATMEL_HLCDC_H__ */
227