1*f6b690e6SBo Shen /* 2*f6b690e6SBo Shen * Header file for AT91/AT32 MULTI LAYER LCD Controller 3*f6b690e6SBo Shen * 4*f6b690e6SBo Shen * Data structure and register user interface 5*f6b690e6SBo Shen * 6*f6b690e6SBo Shen * Copyright (C) 2012 Atmel Corporation 7*f6b690e6SBo Shen * 8*f6b690e6SBo Shen * This program is free software; you can redistribute it and/or modify 9*f6b690e6SBo Shen * it under the terms of the GNU General Public License as published by 10*f6b690e6SBo Shen * the Free Software Foundation; either version 2 of the License, or 11*f6b690e6SBo Shen * (at your option) any later version. 12*f6b690e6SBo Shen * 13*f6b690e6SBo Shen * This program is distributed in the hope that it will be useful, 14*f6b690e6SBo Shen * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*f6b690e6SBo Shen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*f6b690e6SBo Shen * GNU General Public License for more details. 17*f6b690e6SBo Shen * 18*f6b690e6SBo Shen * You should have received a copy of the GNU General Public License 19*f6b690e6SBo Shen * along with this program; if not, write to the Free Software 20*f6b690e6SBo Shen * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21*f6b690e6SBo Shen */ 22*f6b690e6SBo Shen #ifndef __ATMEL_HLCDC_H__ 23*f6b690e6SBo Shen #define __ATMEL_HLCDC_H__ 24*f6b690e6SBo Shen 25*f6b690e6SBo Shen /* Atmel multi layer lcdc hardware registers */ 26*f6b690e6SBo Shen struct atmel_hlcd_regs { 27*f6b690e6SBo Shen u32 lcdc_lcdcfg0; 28*f6b690e6SBo Shen u32 lcdc_lcdcfg1; 29*f6b690e6SBo Shen u32 lcdc_lcdcfg2; 30*f6b690e6SBo Shen u32 lcdc_lcdcfg3; 31*f6b690e6SBo Shen u32 lcdc_lcdcfg4; 32*f6b690e6SBo Shen u32 lcdc_lcdcfg5; 33*f6b690e6SBo Shen u32 lcdc_lcdcfg6; 34*f6b690e6SBo Shen u32 res1; 35*f6b690e6SBo Shen u32 lcdc_lcden; 36*f6b690e6SBo Shen u32 lcdc_lcddis; 37*f6b690e6SBo Shen u32 lcdc_lcdsr; 38*f6b690e6SBo Shen u32 res2; 39*f6b690e6SBo Shen u32 lcdc_lcdidr; 40*f6b690e6SBo Shen u32 res3[3]; 41*f6b690e6SBo Shen u32 lcdc_basecher; 42*f6b690e6SBo Shen u32 res4[3]; 43*f6b690e6SBo Shen u32 lcdc_baseidr; 44*f6b690e6SBo Shen u32 res5[3]; 45*f6b690e6SBo Shen u32 lcdc_baseaddr; 46*f6b690e6SBo Shen u32 lcdc_basectrl; 47*f6b690e6SBo Shen u32 lcdc_basenext; 48*f6b690e6SBo Shen u32 lcdc_basecfg0; 49*f6b690e6SBo Shen u32 lcdc_basecfg1; 50*f6b690e6SBo Shen u32 lcdc_basecfg2; 51*f6b690e6SBo Shen u32 lcdc_basecfg3; 52*f6b690e6SBo Shen u32 lcdc_basecfg4; 53*f6b690e6SBo Shen }; 54*f6b690e6SBo Shen 55*f6b690e6SBo Shen #define LCDC_LCDCFG0_CLKPOL (0x1 << 0) 56*f6b690e6SBo Shen #define LCDC_LCDCFG0_CLKSEL (0x1 << 2) 57*f6b690e6SBo Shen #define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) 58*f6b690e6SBo Shen #define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) 59*f6b690e6SBo Shen #define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) 60*f6b690e6SBo Shen #define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) 61*f6b690e6SBo Shen #define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) 62*f6b690e6SBo Shen #define LCDC_LCDCFG0_CLKDIV_Pos 16 63*f6b690e6SBo Shen #define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos) 64*f6b690e6SBo Shen #define LCDC_LCDCFG0_CLKDIV(value) \ 65*f6b690e6SBo Shen ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos))) 66*f6b690e6SBo Shen 67*f6b690e6SBo Shen #define LCDC_LCDCFG1_HSPW_Pos 0 68*f6b690e6SBo Shen #define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos) 69*f6b690e6SBo Shen #define LCDC_LCDCFG1_HSPW(value) \ 70*f6b690e6SBo Shen ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos))) 71*f6b690e6SBo Shen #define LCDC_LCDCFG1_VSPW_Pos 16 72*f6b690e6SBo Shen #define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos) 73*f6b690e6SBo Shen #define LCDC_LCDCFG1_VSPW(value) \ 74*f6b690e6SBo Shen ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos))) 75*f6b690e6SBo Shen 76*f6b690e6SBo Shen #define LCDC_LCDCFG2_VFPW_Pos 0 77*f6b690e6SBo Shen #define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos) 78*f6b690e6SBo Shen #define LCDC_LCDCFG2_VFPW(value) \ 79*f6b690e6SBo Shen ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos))) 80*f6b690e6SBo Shen #define LCDC_LCDCFG2_VBPW_Pos 16 81*f6b690e6SBo Shen #define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos) 82*f6b690e6SBo Shen #define LCDC_LCDCFG2_VBPW(value) \ 83*f6b690e6SBo Shen ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos))) 84*f6b690e6SBo Shen 85*f6b690e6SBo Shen #define LCDC_LCDCFG3_HFPW_Pos 0 86*f6b690e6SBo Shen #define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos) 87*f6b690e6SBo Shen #define LCDC_LCDCFG3_HFPW(value) \ 88*f6b690e6SBo Shen ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos))) 89*f6b690e6SBo Shen #define LCDC_LCDCFG3_HBPW_Pos 16 90*f6b690e6SBo Shen #define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos) 91*f6b690e6SBo Shen #define LCDC_LCDCFG3_HBPW(value) \ 92*f6b690e6SBo Shen ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos))) 93*f6b690e6SBo Shen 94*f6b690e6SBo Shen #define LCDC_LCDCFG4_PPL_Pos 0 95*f6b690e6SBo Shen #define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos) 96*f6b690e6SBo Shen #define LCDC_LCDCFG4_PPL(value) \ 97*f6b690e6SBo Shen ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos))) 98*f6b690e6SBo Shen #define LCDC_LCDCFG4_RPF_Pos 16 99*f6b690e6SBo Shen #define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos) 100*f6b690e6SBo Shen #define LCDC_LCDCFG4_RPF(value) \ 101*f6b690e6SBo Shen ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos))) 102*f6b690e6SBo Shen 103*f6b690e6SBo Shen #define LCDC_LCDCFG5_HSPOL (0x1 << 0) 104*f6b690e6SBo Shen #define LCDC_LCDCFG5_VSPOL (0x1 << 1) 105*f6b690e6SBo Shen #define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) 106*f6b690e6SBo Shen #define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) 107*f6b690e6SBo Shen #define LCDC_LCDCFG5_DISPPOL (0x1 << 4) 108*f6b690e6SBo Shen #define LCDC_LCDCFG5_SERIAL (0x1 << 5) 109*f6b690e6SBo Shen #define LCDC_LCDCFG5_DITHER (0x1 << 6) 110*f6b690e6SBo Shen #define LCDC_LCDCFG5_DISPDLY (0x1 << 7) 111*f6b690e6SBo Shen #define LCDC_LCDCFG5_MODE_Pos 8 112*f6b690e6SBo Shen #define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos) 113*f6b690e6SBo Shen #define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) 114*f6b690e6SBo Shen #define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) 115*f6b690e6SBo Shen #define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) 116*f6b690e6SBo Shen #define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) 117*f6b690e6SBo Shen #define LCDC_LCDCFG5_VSPSU (0x1 << 12) 118*f6b690e6SBo Shen #define LCDC_LCDCFG5_VSPHO (0x1 << 13) 119*f6b690e6SBo Shen #define LCDC_LCDCFG5_GUARDTIME_Pos 16 120*f6b690e6SBo Shen #define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos) 121*f6b690e6SBo Shen #define LCDC_LCDCFG5_GUARDTIME(value) \ 122*f6b690e6SBo Shen ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos))) 123*f6b690e6SBo Shen 124*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMPS_Pos 0 125*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos) 126*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMPS(value) \ 127*f6b690e6SBo Shen ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos))) 128*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMPOL (0x1 << 4) 129*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMCVAL_Pos 8 130*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos) 131*f6b690e6SBo Shen #define LCDC_LCDCFG6_PWMCVAL(value) \ 132*f6b690e6SBo Shen ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos))) 133*f6b690e6SBo Shen 134*f6b690e6SBo Shen #define LCDC_LCDEN_CLKEN (0x1 << 0) 135*f6b690e6SBo Shen #define LCDC_LCDEN_SYNCEN (0x1 << 1) 136*f6b690e6SBo Shen #define LCDC_LCDEN_DISPEN (0x1 << 2) 137*f6b690e6SBo Shen #define LCDC_LCDEN_PWMEN (0x1 << 3) 138*f6b690e6SBo Shen 139*f6b690e6SBo Shen #define LCDC_LCDDIS_CLKDIS (0x1 << 0) 140*f6b690e6SBo Shen #define LCDC_LCDDIS_SYNCDIS (0x1 << 1) 141*f6b690e6SBo Shen #define LCDC_LCDDIS_DISPDIS (0x1 << 2) 142*f6b690e6SBo Shen #define LCDC_LCDDIS_PWMDIS (0x1 << 3) 143*f6b690e6SBo Shen #define LCDC_LCDDIS_CLKRST (0x1 << 8) 144*f6b690e6SBo Shen #define LCDC_LCDDIS_SYNCRST (0x1 << 9) 145*f6b690e6SBo Shen #define LCDC_LCDDIS_DISPRST (0x1 << 10) 146*f6b690e6SBo Shen #define LCDC_LCDDIS_PWMRST (0x1 << 11) 147*f6b690e6SBo Shen 148*f6b690e6SBo Shen #define LCDC_LCDSR_CLKSTS (0x1 << 0) 149*f6b690e6SBo Shen #define LCDC_LCDSR_LCDSTS (0x1 << 1) 150*f6b690e6SBo Shen #define LCDC_LCDSR_DISPSTS (0x1 << 2) 151*f6b690e6SBo Shen #define LCDC_LCDSR_PWMSTS (0x1 << 3) 152*f6b690e6SBo Shen #define LCDC_LCDSR_SIPSTS (0x1 << 4) 153*f6b690e6SBo Shen 154*f6b690e6SBo Shen #define LCDC_LCDIDR_SOFID (0x1 << 0) 155*f6b690e6SBo Shen #define LCDC_LCDIDR_DISID (0x1 << 1) 156*f6b690e6SBo Shen #define LCDC_LCDIDR_DISPID (0x1 << 2) 157*f6b690e6SBo Shen #define LCDC_LCDIDR_FIFOERRID (0x1 << 4) 158*f6b690e6SBo Shen #define LCDC_LCDIDR_BASEID (0x1 << 8) 159*f6b690e6SBo Shen #define LCDC_LCDIDR_OVR1ID (0x1 << 9) 160*f6b690e6SBo Shen #define LCDC_LCDIDR_HEOID (0x1 << 11) 161*f6b690e6SBo Shen #define LCDC_LCDIDR_HCRID (0x1 << 12) 162*f6b690e6SBo Shen 163*f6b690e6SBo Shen #define LCDC_BASECHER_CHEN (0x1 << 0) 164*f6b690e6SBo Shen #define LCDC_BASECHER_UPDATEEN (0x1 << 1) 165*f6b690e6SBo Shen #define LCDC_BASECHER_A2QEN (0x1 << 2) 166*f6b690e6SBo Shen 167*f6b690e6SBo Shen #define LCDC_BASEIDR_DMA (0x1 << 2) 168*f6b690e6SBo Shen #define LCDC_BASEIDR_DSCR (0x1 << 3) 169*f6b690e6SBo Shen #define LCDC_BASEIDR_ADD (0x1 << 4) 170*f6b690e6SBo Shen #define LCDC_BASEIDR_DONE (0x1 << 5) 171*f6b690e6SBo Shen #define LCDC_BASEIDR_OVR (0x1 << 6) 172*f6b690e6SBo Shen 173*f6b690e6SBo Shen #define LCDC_BASECTRL_DFETCH (0x1 << 0) 174*f6b690e6SBo Shen #define LCDC_BASECTRL_LFETCH (0x1 << 1) 175*f6b690e6SBo Shen #define LCDC_BASECTRL_DMAIEN (0x1 << 2) 176*f6b690e6SBo Shen #define LCDC_BASECTRL_DSCRIEN (0x1 << 3) 177*f6b690e6SBo Shen #define LCDC_BASECTRL_ADDIEN (0x1 << 4) 178*f6b690e6SBo Shen #define LCDC_BASECTRL_DONEIEN (0x1 << 5) 179*f6b690e6SBo Shen 180*f6b690e6SBo Shen #define LCDC_BASECFG0_BLEN_Pos 4 181*f6b690e6SBo Shen #define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) 182*f6b690e6SBo Shen #define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) 183*f6b690e6SBo Shen #define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) 184*f6b690e6SBo Shen #define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) 185*f6b690e6SBo Shen #define LCDC_BASECFG0_DLBO (0x1 << 8) 186*f6b690e6SBo Shen 187*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) 188*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) 189*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) 190*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) 191*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) 192*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) 193*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) 194*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) 195*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) 196*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) 197*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) 198*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) 199*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) 200*f6b690e6SBo Shen #define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) 201*f6b690e6SBo Shen 202*f6b690e6SBo Shen #define LCDC_BASECFG2_XSTRIDE_Pos 0 203*f6b690e6SBo Shen #define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos) 204*f6b690e6SBo Shen #define LCDC_BASECFG2_XSTRIDE(value) \ 205*f6b690e6SBo Shen ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos))) 206*f6b690e6SBo Shen 207*f6b690e6SBo Shen #define LCDC_BASECFG3_BDEF_Pos 0 208*f6b690e6SBo Shen #define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos) 209*f6b690e6SBo Shen #define LCDC_BASECFG3_BDEF(value) \ 210*f6b690e6SBo Shen ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos))) 211*f6b690e6SBo Shen #define LCDC_BASECFG3_GDEF_Pos 8 212*f6b690e6SBo Shen #define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos) 213*f6b690e6SBo Shen #define LCDC_BASECFG3_GDEF(value) \ 214*f6b690e6SBo Shen ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos))) 215*f6b690e6SBo Shen #define LCDC_BASECFG3_RDEF_Pos 16 216*f6b690e6SBo Shen #define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos) 217*f6b690e6SBo Shen #define LCDC_BASECFG3_RDEF(value) \ 218*f6b690e6SBo Shen ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos))) 219*f6b690e6SBo Shen 220*f6b690e6SBo Shen #define LCDC_BASECFG4_DMA (0x1 << 8) 221*f6b690e6SBo Shen #define LCDC_BASECFG4_REP (0x1 << 9) 222*f6b690e6SBo Shen 223*f6b690e6SBo Shen struct lcd_dma_desc { 224*f6b690e6SBo Shen u32 address; 225*f6b690e6SBo Shen u32 control; 226*f6b690e6SBo Shen u32 next; 227*f6b690e6SBo Shen }; 228*f6b690e6SBo Shen 229*f6b690e6SBo Shen #define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4)) 230*f6b690e6SBo Shen 231*f6b690e6SBo Shen #endif /* __ATMEL_HLCDC_H__ */ 232