1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * (C) Copyright 2002-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __ASM_GENERIC_GBL_DATA_H 26 #define __ASM_GENERIC_GBL_DATA_H 27 /* 28 * The following data structure is placed in some memory which is 29 * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or 30 * some locked parts of the data cache) to allow for a minimum set of 31 * global variables during system initialization (until we have set 32 * up the memory controller so that we can use RAM). 33 * 34 * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) 35 * 36 * Each architecture has its own private fields. For now all are private 37 */ 38 39 #ifndef __ASSEMBLY__ 40 typedef struct global_data { 41 bd_t *bd; 42 unsigned long flags; 43 unsigned int baudrate; 44 unsigned long cpu_clk; /* CPU clock in Hz! */ 45 unsigned long bus_clk; 46 /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ 47 unsigned long pci_clk; 48 unsigned long mem_clk; 49 #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) 50 unsigned long fb_base; /* Base address of framebuffer mem */ 51 #endif 52 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) 53 unsigned long post_log_word; /* Record POST activities */ 54 unsigned long post_log_res; /* success of POST test */ 55 unsigned long post_init_f_time; /* When post_init_f started */ 56 #endif 57 #ifdef CONFIG_BOARD_TYPES 58 unsigned long board_type; 59 #endif 60 unsigned long have_console; /* serial_init() was called */ 61 #ifdef CONFIG_PRE_CONSOLE_BUFFER 62 unsigned long precon_buf_idx; /* Pre-Console buffer index */ 63 #endif 64 #ifdef CONFIG_MODEM_SUPPORT 65 unsigned long do_mdm_init; 66 unsigned long be_quiet; 67 #endif 68 unsigned long env_addr; /* Address of Environment struct */ 69 unsigned long env_valid; /* Checksum of Environment valid? */ 70 71 unsigned long ram_top; /* Top address of RAM used by U-Boot */ 72 73 unsigned long relocaddr; /* Start address of U-Boot in RAM */ 74 phys_size_t ram_size; /* RAM size */ 75 unsigned long mon_len; /* monitor len */ 76 unsigned long irq_sp; /* irq stack pointer */ 77 unsigned long start_addr_sp; /* start_addr_stackpointer */ 78 unsigned long reloc_off; 79 struct global_data *new_gd; /* relocated global data */ 80 const void *fdt_blob; /* Our device tree, NULL if none */ 81 void *new_fdt; /* Relocated FDT */ 82 unsigned long fdt_size; /* Space reserved for relocated FDT */ 83 void **jt; /* jump table */ 84 char env_buf[32]; /* buffer for getenv() before reloc. */ 85 struct arch_global_data arch; /* architecture-specific data */ 86 } gd_t; 87 #endif 88 89 /* 90 * Global Data Flags 91 */ 92 #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ 93 #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ 94 #define GD_FLG_SILENT 0x00004 /* Silent mode */ 95 #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ 96 #define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ 97 #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ 98 #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ 99 #define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */ 100 101 #endif /* __ASM_GENERIC_GBL_DATA_H */ 102