1 /* 2 * (C) Copyright 2005 3 * ARM Ltd. 4 * Peter Pearse, <Peter.Pearse@arm.com> 5 * Configuration for ARM Core Modules. 6 * No standalonw port yet available 7 * - this file is included by both integratorap.h & integratorcp.h 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __ARMCOREMODULE_H 29 #define __ARMCOREMODULE_H 30 31 #define CM_BASE 0x10000000 32 33 /* CM registers common to all CMs */ 34 /* Note that observed values after reboot into the ARM Boot Monitor 35 have been used as defaults, rather than the POR values */ 36 #define OS_CTRL 0x0000000C 37 #define CMMASK_REMAP 0x00000005 /* set remap & led */ 38 #define CMMASK_RESET 0x00000008 39 #define OS_LOCK 0x00000014 40 #define CMVAL_LOCK1 0x0000A000 /* locking value */ 41 #define CMVAL_LOCK2 0x0000005F /* locking value */ 42 #define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ 43 #define OS_SDRAM 0x00000020 44 #define OS_INIT 0x00000024 45 #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ 46 #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ 47 #define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ 48 #define CMMASK_LE 0xFFFFFFF7 /* little endian */ 49 #define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */ 50 /* - observed reset value of */ 51 /* CM926EJ-S */ 52 /* CM1136-EJ-S */ 53 54 #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) 55 #define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */ 56 /* - PLL test clock bypassed */ 57 /* - bus clock ratio 2 */ 58 /* - little endian */ 59 /* - vectors at zero */ 60 #endif /* CM1022xx */ 61 62 /* Determine CM characteristics */ 63 64 #undef CONFIG_CM_MULTIPLE_SSRAM 65 #undef CONFIG_CM_SPD_DETECT 66 #undef CONFIG_CM_REMAP 67 #undef CONFIG_CM_INIT 68 #undef CONFIG_CM_TCRAM 69 70 #if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S) 71 #define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */ 72 #endif 73 74 /* Excalibur core module has reduced functionality */ 75 #ifndef CONFIG_CM922T_XA10 76 #define CONFIG_CM_SPD_DETECT /* CM supports SPD query */ 77 #define OS_SPD 0x00000100 /* Address of SPD data */ 78 #define CONFIG_CM_REMAP /* CM supports remapping */ 79 #define CONFIG_CM_INIT /* CM has initialization reg */ 80 #endif /* NOT EXCALIBUR */ 81 82 #if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \ 83 defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \ 84 defined(CONFIG_CM1136JF_S) 85 #define CONFIG_CM_TCRAM /* CM has TCRAM */ 86 #endif 87 88 #ifdef CONFIG_CM_SPD_DETECT 89 #define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ 90 #endif 91 92 #endif /* __ARMCOREMODULE_H */ 93