1 /* 2 * (C) Copyright 2011 Andes Technology Corp 3 * Macpaul Lin <macpaul@andestech.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Andes Power Control Unit 10 */ 11 #ifndef __ANDES_PCU_H 12 #define __ANDES_PCU_H 13 14 #ifndef __ASSEMBLY__ 15 16 struct pcs { 17 unsigned int cr; /* PCSx Configuration (clock scaling) */ 18 unsigned int parm; /* PCSx Parameter*/ 19 unsigned int stat1; /* PCSx Status 1 */ 20 unsigned int stat2; /* PCSx Stusts 2 */ 21 unsigned int pdd; /* PCSx PDD */ 22 }; 23 24 struct andes_pcu { 25 unsigned int rev; /* 0x00 - PCU Revision */ 26 unsigned int spinfo; /* 0x04 - Scratch Pad Info */ 27 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ 28 unsigned int soc_id; /* 0x10 - SoC ID */ 29 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ 30 unsigned int soc_apb; /* 0x18 - SoC APB configuration */ 31 unsigned int rsvd2; /* 0x1C */ 32 unsigned int dcsrcr0; /* 0x20 - Driving Capability 33 and Slew Rate Control 0 */ 34 unsigned int dcsrcr1; /* 0x24 - Driving Capability 35 and Slew Rate Control 1 */ 36 unsigned int dcsrcr2; /* 0x28 - Driving Capability 37 and Slew Rate Control 2 */ 38 unsigned int rsvd3; /* 0x2C */ 39 unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ 40 unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ 41 unsigned int dmaes; /* 0x38 - DMA Engine Selection */ 42 unsigned int rsvd4; /* 0x3C */ 43 unsigned int oscc; /* 0x40 - OSC Control */ 44 unsigned int pwmcd; /* 0x44 - PWM Clock divider */ 45 unsigned int socmisc; /* 0x48 - SoC Misc. */ 46 unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ 47 unsigned int bsmcr; /* 0x80 - BSM Controrl */ 48 unsigned int bsmst; /* 0x84 - BSM Status */ 49 unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ 50 unsigned int west; /* 0x8C - Wakeup Event Status */ 51 unsigned int rsttiming; /* 0x90 - Reset Timing */ 52 unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ 53 unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ 54 struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ 55 unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ 56 struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ 57 unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ 58 struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ 59 unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ 60 struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ 61 unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ 62 struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ 63 unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ 64 struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ 65 unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ 66 struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ 67 unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ 68 struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ 69 unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ 70 struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ 71 unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ 72 unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager 73 Scratch Pad Memory 0 */ 74 }; 75 #endif /* __ASSEMBLY__ */ 76 77 /* 78 * PCU Revision Register (ro) 79 */ 80 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) 81 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) 82 83 /* 84 * Scratch Pad Info Register (ro) 85 */ 86 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) 87 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) 88 89 /* 90 * SoC ID Register (ro) 91 */ 92 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) 93 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) 94 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) 95 96 /* 97 * SoC AHB Configuration Register (ro) 98 */ 99 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) 100 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) 101 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) 102 #define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) 103 #define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) 104 #define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) 105 #define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) 106 #define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) 107 #define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) 108 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) 109 #define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) 110 #define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) 111 #define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) 112 #define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) 113 #define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) 114 #define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) 115 #define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) 116 #define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) 117 #define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) 118 #define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) 119 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) 120 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) 121 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) 122 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) 123 124 /* 125 * SoC APB Configuration Register (ro) 126 */ 127 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) 128 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) 129 #define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) 130 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) 131 #define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) 132 #define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) 133 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) 134 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) 135 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) 136 #define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) 137 #define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) 138 #define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) 139 #define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) 140 141 /* 142 * Driving Capability and Slew Rate Control Register 0 (rw) 143 */ 144 #define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) 145 #define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) 146 #define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) 147 #define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) 148 #define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) 149 150 /* 151 * Driving Capability and Slew Rate Control Register 1 (rw) 152 */ 153 #define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) 154 155 /* 156 * Driving Capability and Slew Rate Control Register 2 (rw) 157 */ 158 #define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) 159 #define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) 160 #define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) 161 #define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) 162 #define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) 163 #define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) 164 #define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) 165 #define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) 166 167 /* 168 * Multi-function Port Setting Register 0 (rw) 169 */ 170 #define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) 171 #define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) 172 #define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) 173 #define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) 174 #define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) 175 #define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) 176 #define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) 177 178 /* 179 * Multi-function Port Setting Register 1 (rw) 180 */ 181 #define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) 182 #define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) 183 #define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) 184 #define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) 185 #define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) 186 #define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) 187 #define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) 188 #define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) 189 #define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) 190 #define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) 191 #define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) 192 #define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) 193 #define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) 194 #define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) 195 #define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) 196 #define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) 197 198 /* 199 * DMA Engine Selection Register (rw) 200 */ 201 #define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) 202 #define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) 203 #define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) 204 #define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) 205 #define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) 206 #define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) 207 #define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) 208 #define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) 209 210 /* 211 * OSC Control Register (rw) 212 */ 213 #define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) 214 #define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) 215 #define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) 216 #define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) 217 #define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) 218 #define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) 219 220 /* 221 * PWM Clock Divider Register (rw) 222 */ 223 #define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) 224 225 /* 226 * SoC Misc. Register (rw) 227 */ 228 #define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) 229 #define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) 230 #define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) 231 #define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) 232 #define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) 233 #define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) 234 #define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) 235 #define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) 236 #define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) 237 #define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) 238 #define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) 239 #define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) 240 #define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) 241 #define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) 242 #define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) 243 #define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) 244 #define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) 245 #define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) 246 #define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) 247 #define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) 248 #define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) 249 #define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) 250 #define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) 251 #define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) 252 #define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) 253 #define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) 254 #define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) 255 #define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) 256 #define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) 257 #define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) 258 259 /* 260 * BSM Control Register (rw) 261 */ 262 #define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) 263 #define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) 264 #define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) 265 #define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) 266 #define ANDES_PCU_BSMCR_IE(x) ((x) << 31) 267 268 /* 269 * BSM Status Register 270 */ 271 #define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) 272 #define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) 273 #define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) 274 #define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) 275 276 /* 277 * Wakeup Event Sensitivity Register (rw) 278 */ 279 #define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) 280 281 /* 282 * Wakeup Event Status Register (ro) 283 */ 284 #define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) 285 286 /* 287 * Reset Timing Register 288 */ 289 #define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) 290 #define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) 291 #define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) 292 #define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) 293 294 /* 295 * PCU Interrupt Status Register 296 */ 297 #define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) 298 #define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) 299 #define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) 300 #define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) 301 #define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) 302 #define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) 303 #define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) 304 #define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) 305 #define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) 306 #define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) 307 308 /* 309 * PCSx Configuration Register 310 */ 311 #define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) 312 #define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) 313 #define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) 314 #define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ 315 316 /* 317 * PCSx Parameter Register (rw) 318 */ 319 #define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) 320 #define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) 321 #define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) 322 #define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) 323 324 /* 325 * PCSx Status Register 1 326 */ 327 #define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) 328 #define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) 329 330 /* 331 * PCSx Status Register 2 332 */ 333 #define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) 334 #define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) 335 336 /* 337 * PCSx PDD Register 338 * This is reserved for PCS(1-7) 339 */ 340 #define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) 341 #define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) 342 #define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) 343 #define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) 344 345 #define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) 346 #define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) 347 #define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) 348 #define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) 349 #define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) 350 #define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) 351 #define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) 352 #define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) 353 #define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) 354 355 #endif /* __ANDES_PCU_H */ 356