1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _MCD_API_H 8 #define _MCD_API_H 9 10 /* Turn Execution Unit tasks ON (#define) or OFF (#undef) */ 11 #undef MCD_INCLUDE_EU 12 13 /* Number of DMA channels */ 14 #define NCHANNELS 16 15 16 /* Total number of variants */ 17 #ifdef MCD_INCLUDE_EU 18 #define NUMOFVARIANTS 6 19 #else 20 #define NUMOFVARIANTS 4 21 #endif 22 23 /* Define sizes of the various tables */ 24 #define TASK_TABLE_SIZE (NCHANNELS*32) 25 #define VAR_TAB_SIZE (128) 26 #define CONTEXT_SAVE_SIZE (128) 27 #define FUNCDESC_TAB_SIZE (256) 28 29 #ifdef MCD_INCLUDE_EU 30 #define FUNCDESC_TAB_NUM 16 31 #else 32 #define FUNCDESC_TAB_NUM 1 33 #endif 34 35 #ifndef DEFINESONLY 36 37 /* Portability typedefs */ 38 #if 1 39 #include "common.h" 40 #else 41 #ifndef s32 42 typedef int s32; 43 #endif 44 #ifndef u32 45 typedef unsigned int u32; 46 #endif 47 #ifndef s16 48 typedef short s16; 49 #endif 50 #ifndef u16 51 typedef unsigned short u16; 52 #endif 53 #ifndef s8 54 typedef char s8; 55 #endif 56 #ifndef u8 57 typedef unsigned char u8; 58 #endif 59 #endif 60 61 /* 62 * These structures represent the internal registers of the 63 * multi-channel DMA 64 */ 65 struct dmaRegs_s { 66 u32 taskbar; /* task table base address */ 67 u32 currPtr; 68 u32 endPtr; 69 u32 varTablePtr; 70 u16 dma_rsvd0; 71 u16 ptdControl; /* ptd control */ 72 u32 intPending; /* interrupt pending */ 73 u32 intMask; /* interrupt mask */ 74 u16 taskControl[16]; /* task control */ 75 u8 priority[32]; /* priority */ 76 u32 initiatorMux; /* initiator mux control */ 77 u32 taskSize0; /* task size control 0. */ 78 u32 taskSize1; /* task size control 1. */ 79 u32 dma_rsvd1; /* reserved */ 80 u32 dma_rsvd2; /* reserved */ 81 u32 debugComp1; /* debug comparator 1 */ 82 u32 debugComp2; /* debug comparator 2 */ 83 u32 debugControl; /* debug control */ 84 u32 debugStatus; /* debug status */ 85 u32 ptdDebug; /* priority task decode debug */ 86 u32 dma_rsvd3[31]; /* reserved */ 87 }; 88 typedef volatile struct dmaRegs_s dmaRegs; 89 90 #endif 91 92 /* PTD contrl reg bits */ 93 #define PTD_CTL_TSK_PRI 0x8000 94 #define PTD_CTL_COMM_PREFETCH 0x0001 95 96 /* Task Control reg bits and field masks */ 97 #define TASK_CTL_EN 0x8000 98 #define TASK_CTL_VALID 0x4000 99 #define TASK_CTL_ALWAYS 0x2000 100 #define TASK_CTL_INIT_MASK 0x1f00 101 #define TASK_CTL_ASTRT 0x0080 102 #define TASK_CTL_HIPRITSKEN 0x0040 103 #define TASK_CTL_HLDINITNUM 0x0020 104 #define TASK_CTL_ASTSKNUM_MASK 0x000f 105 106 /* Priority reg bits and field masks */ 107 #define PRIORITY_HLD 0x80 108 #define PRIORITY_PRI_MASK 0x07 109 110 /* Debug Control reg bits and field masks */ 111 #define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 112 #define DBG_CTL_AUTO_ARM 0x00008000 113 #define DBG_CTL_BREAK 0x00004000 114 #define DBG_CTL_COMP1_TYP_MASK 0x00003800 115 #define DBG_CTL_COMP2_TYP_MASK 0x00000070 116 #define DBG_CTL_EXT_BREAK 0x00000004 117 #define DBG_CTL_INT_BREAK 0x00000002 118 119 /* 120 * PTD Debug reg selector addresses 121 * This reg must be written with a value to show the contents of 122 * one of the desired internal register. 123 */ 124 #define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ 125 #define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and 126 have initiators asserted */ 127 128 /* General return values */ 129 #define MCD_OK 0 130 #define MCD_ERROR -1 131 #define MCD_TABLE_UNALIGNED -2 132 #define MCD_CHANNEL_INVALID -3 133 134 /* MCD_initDma input flags */ 135 #define MCD_RELOC_TASKS 0x00000001 136 #define MCD_NO_RELOC_TASKS 0x00000000 137 #define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */ 138 139 /* 140 * MCD_dmaStatus Status Values for each channel: 141 * MCD_NO_DMA - No DMA has been requested since reset 142 * MCD_IDLE - DMA active, but the initiator is currently inactive 143 * MCD_RUNNING - DMA active, and the initiator is currently active 144 * MCD_PAUSED - DMA active but it is currently paused 145 * MCD_HALTED - the most recent DMA has been killed with MCD_killTask() 146 * MCD_DONE - the most recent DMA has completed 147 */ 148 #define MCD_NO_DMA 1 149 #define MCD_IDLE 2 150 #define MCD_RUNNING 3 151 #define MCD_PAUSED 4 152 #define MCD_HALTED 5 153 #define MCD_DONE 6 154 155 /* MCD_startDma parameter defines */ 156 157 /* Constants for the funcDesc parameter */ 158 /* 159 * MCD_NO_BYTE_SWAP - to disable byte swapping 160 * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data 161 * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data 162 * value being DMAed 163 * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of 164 * each 32-bit data value DMAed 165 * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed 166 * MCD_BIT_REV - reverse the bits of each byte DMAed 167 * MCD_CRC16 - to perform CRC-16 on DMAed data 168 * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data 169 * MCD_CRC32 - to perform CRC-32 on DMAed data 170 * MCD_CSUMINET - to perform internet checksums on DMAed data 171 * MCD_NO_CSUM - to perform no checksumming 172 */ 173 #define MCD_NO_BYTE_SWAP 0x00045670 174 #define MCD_BYTE_REVERSE 0x00076540 175 #define MCD_U16_REVERSE 0x00067450 176 #define MCD_U16_BYTE_REVERSE 0x00054760 177 #define MCD_NO_BIT_REV 0x00000000 178 #define MCD_BIT_REV 0x00088880 179 /* CRCing: */ 180 #define MCD_CRC16 0xc0100000 181 #define MCD_CRCCCITT 0xc0200000 182 #define MCD_CRC32 0xc0300000 183 #define MCD_CSUMINET 0xc0400000 184 #define MCD_NO_CSUM 0xa0000000 185 186 #define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \ 187 MCD_NO_CSUM) 188 #define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) 189 190 /* Constants for the flags parameter */ 191 #define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ 192 #define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ 193 #define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */ 194 #define MCD_TT_FLAGS_MASK 0x000000ff 195 #define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) 196 197 #define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ 198 #define MCD_CHAIN_DMA /* TBD */ 199 #define MCD_EU_DMA /* TBD */ 200 #define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ 201 #define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ 202 203 /* these flags are valid for MCD_startDma and the chained buffer descriptors */ 204 /* 205 * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl 206 * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD 207 * MCD_INTERRUPT - to generate an interrupt after completion of the DMA 208 * MCD_END_FRAME - tell the DMA to end the frame when transferring 209 * last byte of data in buffer 210 * MCD_CRC_RESTART - to empty out the accumulated checksum prior to 211 * performing the DMA 212 */ 213 #define MCD_BUF_READY 0x80000000 214 #define MCD_WRAP 0x20000000 215 #define MCD_INTERRUPT 0x10000000 216 #define MCD_END_FRAME 0x08000000 217 #define MCD_CRC_RESTART 0x40000000 218 219 /* Defines for the FEC buffer descriptor control/status word*/ 220 #define MCD_FEC_BUF_READY 0x8000 221 #define MCD_FEC_WRAP 0x2000 222 #define MCD_FEC_INTERRUPT 0x1000 223 #define MCD_FEC_END_FRAME 0x0800 224 225 /* Defines for general intuitiveness */ 226 227 #define MCD_TRUE 1 228 #define MCD_FALSE 0 229 230 /* Three different cases for destination and source. */ 231 #define MINUS1 -1 232 #define ZERO 0 233 #define PLUS1 1 234 235 #ifndef DEFINESONLY 236 237 /* Task Table Entry struct*/ 238 typedef struct { 239 u32 TDTstart; /* task descriptor table start */ 240 u32 TDTend; /* task descriptor table end */ 241 u32 varTab; /* variable table start */ 242 u32 FDTandFlags; /* function descriptor table start & flags */ 243 volatile u32 descAddrAndStatus; 244 volatile u32 modifiedVarTab; 245 u32 contextSaveSpace; /* context save space start */ 246 u32 literalBases; 247 } TaskTableEntry; 248 249 /* Chained buffer descriptor: 250 * flags - flags describing the DMA 251 * csumResult - checksum performed since last checksum reset 252 * srcAddr - the address to move data from 253 * destAddr - the address to move data to 254 * lastDestAddr - the last address written to 255 * dmaSize - the no of bytes to xfer independent of the xfer sz 256 * next - next buffer descriptor in chain 257 * info - private info about this descriptor; DMA does not affect it 258 */ 259 typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; 260 struct MCD_bufDesc_struct { 261 u32 flags; 262 u32 csumResult; 263 s8 *srcAddr; 264 s8 *destAddr; 265 s8 *lastDestAddr; 266 u32 dmaSize; 267 MCD_bufDesc *next; 268 u32 info; 269 }; 270 271 /* Progress Query struct: 272 * lastSrcAddr - the most-recent or last, post-increment source address 273 * lastDestAddr - the most-recent or last, post-increment destination address 274 * dmaSize - the amount of data transferred for the current buffer 275 * currBufDesc - pointer to the current buffer descriptor being DMAed 276 */ 277 278 typedef volatile struct MCD_XferProg_struct { 279 s8 *lastSrcAddr; 280 s8 *lastDestAddr; 281 u32 dmaSize; 282 MCD_bufDesc *currBufDesc; 283 } MCD_XferProg; 284 285 /* FEC buffer descriptor */ 286 typedef volatile struct MCD_bufDescFec_struct { 287 u16 statCtrl; 288 u16 length; 289 u32 dataPointer; 290 } MCD_bufDescFec; 291 292 /*************************************************************************/ 293 /* API function Prototypes - see MCD_dmaApi.c for further notes */ 294 295 /* MCD_startDma starts a particular kind of DMA: 296 * srcAddr - the channel on which to run the DMA 297 * srcIncr - the address to move data from, or buffer-descriptor address 298 * destAddr - the amount to increment the source address per transfer 299 * destIncr - the address to move data to 300 * dmaSize - the amount to increment the destination address per transfer 301 * xferSize - the number bytes in of each data movement (1, 2, or 4) 302 * initiator - what device initiates the DMA 303 * priority - priority of the DMA 304 * flags - flags describing the DMA 305 * funcDesc - description of byte swapping, bit swapping, and CRC actions 306 */ 307 int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr, 308 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, 309 int priority, u32 flags, u32 funcDesc); 310 311 /* 312 * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA 313 * registers, relocating and creating the appropriate task structures, and 314 * setting up some global settings 315 */ 316 int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags); 317 318 /* MCD_dmaStatus() returns the status of the DMA on the requested channel. */ 319 int MCD_dmaStatus(int channel); 320 321 /* MCD_XferProgrQuery() returns progress of DMA on requested channel */ 322 int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep); 323 324 /* 325 * MCD_killDma() halts the DMA on the requested channel, without any 326 * intention of resuming the DMA. 327 */ 328 int MCD_killDma(int channel); 329 330 /* 331 * MCD_continDma() continues a DMA which as stopped due to encountering an 332 * unready buffer descriptor. 333 */ 334 int MCD_continDma(int channel); 335 336 /* 337 * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is 338 * running on that channel). 339 */ 340 int MCD_pauseDma(int channel); 341 342 /* 343 * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is 344 * running on that channel). 345 */ 346 int MCD_resumeDma(int channel); 347 348 /* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */ 349 int MCD_csumQuery(int channel, u32 * csum); 350 351 /* 352 * MCD_getCodeSize provides the packed size required by the microcoded task 353 * and structures. 354 */ 355 int MCD_getCodeSize(void); 356 357 /* 358 * MCD_getVersion provides a pointer to a version string and returns a 359 * version number. 360 */ 361 int MCD_getVersion(char **longVersion); 362 363 /* macro for setting a location in the variable table */ 364 #define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value 365 /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, 366 so I'm avoiding surrounding it with "do {} while(0)" */ 367 368 #endif /* DEFINESONLY */ 369 370 #endif /* _MCD_API_H */ 371