1 /*
2  * Copyright (c) 2011-2013 Xilinx Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/microblaze_intc.h>
26 #include <asm/processor.h>
27 #include <watchdog.h>
28 
29 #define XWT_CSR0_WRS_MASK	0x00000008 /* Reset status Mask */
30 #define XWT_CSR0_WDS_MASK	0x00000004 /* Timer state Mask */
31 #define XWT_CSR0_EWDT1_MASK	0x00000002 /* Enable bit 1 Mask*/
32 #define XWT_CSRX_EWDT2_MASK	0x00000001 /* Enable bit 2 Mask */
33 
34 struct watchdog_regs {
35 	u32 twcsr0; /* 0x0 */
36 	u32 twcsr1; /* 0x4 */
37 	u32 tbr; /* 0x8 */
38 };
39 
40 static struct watchdog_regs *watchdog_base =
41 			(struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
42 
43 void hw_watchdog_reset(void)
44 {
45 	u32 reg;
46 
47 	/* Read the current contents of TCSR0 */
48 	reg = readl(&watchdog_base->twcsr0);
49 
50 	/* Clear the watchdog WDS bit */
51 	if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
52 		writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
53 }
54 
55 void hw_watchdog_disable(void)
56 {
57 	u32 reg;
58 
59 	/* Read the current contents of TCSR0 */
60 	reg = readl(&watchdog_base->twcsr0);
61 
62 	writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
63 	writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
64 
65 	puts("Watchdog disabled!\n");
66 }
67 
68 static void hw_watchdog_isr(void *arg)
69 {
70 	hw_watchdog_reset();
71 }
72 
73 int hw_watchdog_init(void)
74 {
75 	int ret;
76 
77 	writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
78 	       &watchdog_base->twcsr0);
79 	writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
80 
81 	ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
82 						hw_watchdog_isr, NULL);
83 	if (ret)
84 		return 1;
85 
86 	return 0;
87 }
88