1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2011-2013 Xilinx Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/microblaze_intc.h>
9 #include <asm/processor.h>
10 #include <watchdog.h>
11 
12 #define XWT_CSR0_WRS_MASK	0x00000008 /* Reset status Mask */
13 #define XWT_CSR0_WDS_MASK	0x00000004 /* Timer state Mask */
14 #define XWT_CSR0_EWDT1_MASK	0x00000002 /* Enable bit 1 Mask*/
15 #define XWT_CSRX_EWDT2_MASK	0x00000001 /* Enable bit 2 Mask */
16 
17 struct watchdog_regs {
18 	u32 twcsr0; /* 0x0 */
19 	u32 twcsr1; /* 0x4 */
20 	u32 tbr; /* 0x8 */
21 };
22 
23 static struct watchdog_regs *watchdog_base =
24 			(struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
25 
26 void hw_watchdog_reset(void)
27 {
28 	u32 reg;
29 
30 	/* Read the current contents of TCSR0 */
31 	reg = readl(&watchdog_base->twcsr0);
32 
33 	/* Clear the watchdog WDS bit */
34 	if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
35 		writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
36 }
37 
38 void hw_watchdog_disable(void)
39 {
40 	u32 reg;
41 
42 	/* Read the current contents of TCSR0 */
43 	reg = readl(&watchdog_base->twcsr0);
44 
45 	writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
46 	writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
47 
48 	puts("Watchdog disabled!\n");
49 }
50 
51 static void hw_watchdog_isr(void *arg)
52 {
53 	hw_watchdog_reset();
54 }
55 
56 void hw_watchdog_init(void)
57 {
58 	int ret;
59 
60 	writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
61 	       &watchdog_base->twcsr0);
62 	writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
63 
64 	ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
65 						hw_watchdog_isr, NULL);
66 	if (ret)
67 		puts("Watchdog IRQ registration failed.");
68 }
69