1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * omap_wdt.c 4 * 5 * (C) Copyright 2013 6 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 7 * 8 * Based on: 9 * 10 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog 11 * 12 * commit 2d991a164a61858012651e13c59521975504e260 13 * Author: Bill Pemberton <wfp5p@virginia.edu> 14 * Date: Mon Nov 19 13:21:41 2012 -0500 15 * 16 * watchdog: remove use of __devinit 17 * 18 * CONFIG_HOTPLUG is going away as an option so __devinit is no longer 19 * needed. 20 * 21 * Author: MontaVista Software, Inc. 22 * <gdavis@mvista.com> or <source@mvista.com> 23 * 24 * History: 25 * 26 * 20030527: George G. Davis <gdavis@mvista.com> 27 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c 28 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> 29 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> 30 * 31 * Copyright (c) 2004 Texas Instruments. 32 * 1. Modified to support OMAP1610 32-KHz watchdog timer 33 * 2. Ported to 2.6 kernel 34 * 35 * Copyright (c) 2005 David Brownell 36 * Use the driver model and standard identifiers; handle bigger timeouts. 37 */ 38 39 #include <common.h> 40 #include <watchdog.h> 41 #include <asm/arch/hardware.h> 42 #include <asm/io.h> 43 #include <asm/processor.h> 44 #include <asm/arch/cpu.h> 45 46 /* Hardware timeout in seconds */ 47 #define WDT_HW_TIMEOUT 60 48 49 static unsigned int wdt_trgr_pattern = 0x1234; 50 51 void hw_watchdog_reset(void) 52 { 53 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; 54 55 /* 56 * Somebody just triggered watchdog reset and write to WTGR register 57 * is in progress. It is resetting right now, no need to trigger it 58 * again 59 */ 60 if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) 61 return; 62 63 wdt_trgr_pattern = ~wdt_trgr_pattern; 64 writel(wdt_trgr_pattern, &wdt->wdtwtgr); 65 66 /* 67 * Don't wait for posted write to complete, i.e. don't check 68 * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to 69 * WTGR register outside of this func, and if entering it 70 * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset 71 * was just triggered. This prevents us from wasting time in busy 72 * polling of WDT_WWPS_PEND_WTGR bit. 73 */ 74 } 75 76 static int omap_wdt_set_timeout(unsigned int timeout) 77 { 78 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; 79 u32 pre_margin = GET_WLDR_VAL(timeout); 80 81 /* just count up at 32 KHz */ 82 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) 83 ; 84 85 writel(pre_margin, &wdt->wdtwldr); 86 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) 87 ; 88 89 return 0; 90 } 91 92 void hw_watchdog_disable(void) 93 { 94 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; 95 96 /* 97 * Disable watchdog 98 */ 99 writel(0xAAAA, &wdt->wdtwspr); 100 while (readl(&wdt->wdtwwps) != 0x0) 101 ; 102 writel(0x5555, &wdt->wdtwspr); 103 while (readl(&wdt->wdtwwps) != 0x0) 104 ; 105 } 106 107 void hw_watchdog_init(void) 108 { 109 struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; 110 111 /* 112 * Make sure the watchdog is disabled. This is unfortunately required 113 * because writing to various registers with the watchdog running has no 114 * effect. 115 */ 116 hw_watchdog_disable(); 117 118 /* initialize prescaler */ 119 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) 120 ; 121 122 writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr); 123 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) 124 ; 125 126 omap_wdt_set_timeout(WDT_HW_TIMEOUT); 127 128 /* Sequence to enable the watchdog */ 129 writel(0xBBBB, &wdt->wdtwspr); 130 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) 131 ; 132 133 writel(0x4444, &wdt->wdtwspr); 134 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) 135 ; 136 } 137