1 /*
2  * watchdog.c - driver for i.mx on-chip watchdog
3  *
4  * Licensed under the GPL-2 or later.
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <watchdog.h>
10 #include <asm/arch/imx-regs.h>
11 #include <fsl_wdog.h>
12 
13 #ifdef CONFIG_IMX_WATCHDOG
14 void hw_watchdog_reset(void)
15 {
16 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
17 
18 	writew(0x5555, &wdog->wsr);
19 	writew(0xaaaa, &wdog->wsr);
20 }
21 
22 void hw_watchdog_init(void)
23 {
24 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
25 	u16 timeout;
26 
27 	/*
28 	 * The timer watchdog can be set between
29 	 * 0.5 and 128 Seconds. If not defined
30 	 * in configuration file, sets 128 Seconds
31 	 */
32 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
33 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
34 #endif
35 	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
36 	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
37 		WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
38 	hw_watchdog_reset();
39 }
40 #endif
41 
42 void __attribute__((weak)) reset_cpu(ulong addr)
43 {
44 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
45 
46 	clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
47 
48 	writew(0x5555, &wdog->wsr);
49 	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */
50 	while (1) {
51 		/*
52 		 * spin for .5 seconds before reset
53 		 */
54 	}
55 }
56