1 /* 2 * watchdog.c - driver for i.mx on-chip watchdog 3 * 4 * Licensed under the GPL-2 or later. 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <watchdog.h> 10 #include <asm/arch/imx-regs.h> 11 #ifdef CONFIG_FSL_LSCH2 12 #include <asm/arch/immap_lsch2.h> 13 #endif 14 #include <fsl_wdog.h> 15 16 #ifdef CONFIG_IMX_WATCHDOG 17 void hw_watchdog_reset(void) 18 { 19 #ifndef CONFIG_WATCHDOG_RESET_DISABLE 20 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 21 22 writew(0x5555, &wdog->wsr); 23 writew(0xaaaa, &wdog->wsr); 24 #endif /* CONFIG_WATCHDOG_RESET_DISABLE*/ 25 } 26 27 void hw_watchdog_init(void) 28 { 29 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 30 u16 timeout; 31 32 /* 33 * The timer watchdog can be set between 34 * 0.5 and 128 Seconds. If not defined 35 * in configuration file, sets 128 Seconds 36 */ 37 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS 38 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 39 #endif 40 timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; 41 #ifdef CONFIG_FSL_LSCH2 42 writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); 43 #else 44 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | 45 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); 46 #endif /* CONFIG_FSL_LSCH2*/ 47 hw_watchdog_reset(); 48 } 49 #endif 50 51 void __attribute__((weak)) reset_cpu(ulong addr) 52 { 53 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 54 55 clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); 56 57 writew(0x5555, &wdog->wsr); 58 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ 59 while (1) { 60 /* 61 * spin for .5 seconds before reset 62 */ 63 } 64 } 65