1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <errno.h> 9 #include <wdt.h> 10 #include <asm/io.h> 11 #include <asm/arch/wdt.h> 12 13 enum aspeed_wdt_model { 14 WDT_AST2400, 15 WDT_AST2500, 16 WDT_AST2600, 17 }; 18 19 struct ast_wdt_priv { 20 struct ast_wdt *regs; 21 }; 22 23 static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags) 24 { 25 struct ast_wdt_priv *priv = dev_get_priv(dev); 26 ulong driver_data = dev_get_driver_data(dev); 27 u32 reset_mode = ast_reset_mode_from_flags(flags); 28 29 clrsetbits_le32(&priv->regs->ctrl, 30 WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT, 31 reset_mode << WDT_CTRL_RESET_MODE_SHIFT); 32 33 if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC) 34 writel(ast_reset_mask_from_flags(flags), 35 &priv->regs->reset_mask); 36 37 writel((u32) timeout, &priv->regs->counter_reload_val); 38 writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart); 39 /* 40 * Setting CLK1MHZ bit is just for compatibility with ast2400 part. 41 * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is 42 * read-only 43 */ 44 setbits_le32(&priv->regs->ctrl, 45 WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ); 46 47 return 0; 48 } 49 50 static int ast_wdt_stop(struct udevice *dev) 51 { 52 struct ast_wdt_priv *priv = dev_get_priv(dev); 53 54 clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN); 55 56 writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask); 57 return 0; 58 } 59 60 static int ast_wdt_reset(struct udevice *dev) 61 { 62 struct ast_wdt_priv *priv = dev_get_priv(dev); 63 64 writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart); 65 66 return 0; 67 } 68 69 static int ast_wdt_expire_now(struct udevice *dev, ulong flags) 70 { 71 struct ast_wdt_priv *priv = dev_get_priv(dev); 72 int ret; 73 74 ret = ast_wdt_start(dev, 1, flags); 75 if (ret) 76 return ret; 77 78 while (readl(&priv->regs->ctrl) & WDT_CTRL_EN) 79 ; 80 81 return ast_wdt_stop(dev); 82 } 83 84 static int ast_wdt_ofdata_to_platdata(struct udevice *dev) 85 { 86 struct ast_wdt_priv *priv = dev_get_priv(dev); 87 88 priv->regs = devfdt_get_addr_ptr(dev); 89 if (IS_ERR(priv->regs)) 90 return PTR_ERR(priv->regs); 91 92 return 0; 93 } 94 95 static const struct wdt_ops ast_wdt_ops = { 96 .start = ast_wdt_start, 97 .reset = ast_wdt_reset, 98 .stop = ast_wdt_stop, 99 .expire_now = ast_wdt_expire_now, 100 }; 101 102 static int ast_wdt_probe(struct udevice *dev) 103 { 104 debug("%s() wdt%u\n", __func__, dev->seq); 105 ast_wdt_stop(dev); 106 107 return 0; 108 } 109 110 static const struct udevice_id ast_wdt_ids[] = { 111 { .compatible = "aspeed,wdt", .data = WDT_AST2500 }, 112 { .compatible = "aspeed,ast2600-wdt", .data = WDT_AST2600 }, 113 { .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 }, 114 { .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 }, 115 {} 116 }; 117 118 U_BOOT_DRIVER(ast_wdt) = { 119 .name = "ast_wdt", 120 .id = UCLASS_WDT, 121 .of_match = ast_wdt_ids, 122 .probe = ast_wdt_probe, 123 .priv_auto_alloc_size = sizeof(struct ast_wdt_priv), 124 .ofdata_to_platdata = ast_wdt_ofdata_to_platdata, 125 .ops = &ast_wdt_ops, 126 }; 127