xref: /openbmc/u-boot/drivers/watchdog/Kconfig (revision 10e40d54)
1menu "Watchdog Timer Support"
2
3config HW_WATCHDOG
4	bool
5
6config BCM2835_WDT
7	bool "Enable BCM2835/2836 watchdog driver"
8	select HW_WATCHDOG
9	help
10	  Say Y here to enable the BCM2835/2836 watchdog
11
12	  This provides basic infrastructure to support BCM2835/2836 watchdog
13	  hardware, with a max timeout of ~15secs.
14
15config OMAP_WATCHDOG
16	bool "TI OMAP watchdog driver"
17	depends on ARCH_OMAP2PLUS
18	select HW_WATCHDOG
19	default y if AM33XX
20	help
21	  Say Y here to enable the OMAP3+ watchdog driver.
22
23config ULP_WATCHDOG
24	bool "i.MX7ULP watchdog"
25	help
26	  Say Y here to enable i.MX7ULP watchdog driver.
27
28config WDT
29	bool "Enable driver model for watchdog timer drivers"
30	depends on DM
31	help
32	  Enable driver model for watchdog timer. At the moment the API
33	  is very simple and only supports four operations:
34	  start, restart, stop and reset (expire immediately).
35	  What exactly happens when the timer expires is up to a particular
36	  device/driver.
37
38config WDT_SANDBOX
39	bool "Enable Watchdog Timer support for Sandbox"
40	depends on SANDBOX && WDT
41	help
42		Enable Watchdog Timer support in Sandbox. This is a dummy device that
43		can be probed and supports all of the methods of WDT, but does not
44		really do anything.
45
46config WDT_ASPEED
47	bool "Aspeed ast2400/ast2500 watchdog timer support"
48	depends on WDT
49	default y if ARCH_ASPEED
50	help
51	  Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
52	  The watchdog timer is stopped when initialized. It performs reset, either
53	  full SoC reset or CPU or just some peripherals, based on the flags.
54	  It currently does not support Boot Flash Addressing Mode Detection or
55	  Second Boot.
56
57config WDT_BCM6345
58	bool "BCM6345 watchdog timer support"
59	depends on WDT && ARCH_BMIPS
60	help
61	  Select this to enable watchdog timer for BCM6345 SoCs.
62	  The watchdog timer is stopped when initialized.
63	  It performs full SoC reset.
64
65endmenu
66