1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014, NVIDIA Corporation. 4 */ 5 6 #ifndef _TEGRA_DISPLAYPORT_H 7 #define _TEGRA_DISPLAYPORT_H 8 9 #include <linux/drm_dp_helper.h> 10 11 struct dpaux_ctlr { 12 u32 reserved0; 13 u32 intr_en_aux; 14 u32 reserved2_4; 15 u32 intr_aux; 16 }; 17 18 #define DPAUX_INTR_EN_AUX 0x1 19 #define DPAUX_INTR_AUX 0x5 20 #define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i)) 21 #define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i)) 22 #define DPAUX_DP_AUXADDR 0x29 23 #define DPAUX_DP_AUXCTL 0x2d 24 #define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0 25 #define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff 26 #define DPAUX_DP_AUXCTL_CMD_SHIFT 12 27 #define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) 28 #define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) 29 #define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) 30 #define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) 31 #define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) 32 #define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) 33 #define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) 34 #define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) 35 #define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) 36 #define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16 37 #define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) 38 #define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) 39 #define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) 40 #define DPAUX_DP_AUXCTL_RST_SHIFT 31 41 #define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) 42 #define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) 43 #define DPAUX_DP_AUXSTAT 0x31 44 #define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28 45 #define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) 46 #define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) 47 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20 48 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) 49 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) 50 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) 51 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) 52 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) 53 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) 54 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) 55 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) 56 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) 57 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) 58 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) 59 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) 60 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) 61 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) 62 #define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16 63 #define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) 64 #define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) 65 #define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) 66 #define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) 67 #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) 68 #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) 69 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11 70 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) 71 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) 72 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10 73 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) 74 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) 75 #define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9 76 #define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) 77 #define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) 78 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8 79 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) 80 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) 81 #define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0 82 #define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) 83 #define DPAUX_HPD_CONFIG (0x3d) 84 #define DPAUX_HPD_IRQ_CONFIG 0x41 85 #define DPAUX_DP_AUX_CONFIG 0x45 86 #define DPAUX_HYBRID_PADCTL 0x49 87 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15 88 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) 89 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) 90 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14 91 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) 92 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) 93 #define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12 94 #define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) 95 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) 96 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) 97 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) 98 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) 99 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8 100 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) 101 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) 102 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) 103 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) 104 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) 105 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) 106 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) 107 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) 108 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) 109 #define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2 110 #define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) 111 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1 112 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) 113 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) 114 #define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0 115 #define DPAUX_HYBRID_PADCTL_MODE_AUX 0 116 #define DPAUX_HYBRID_PADCTL_MODE_I2C 1 117 #define DPAUX_HYBRID_SPARE 0x4d 118 #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0 119 #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1 120 121 #define DP_AUX_DEFER_MAX_TRIES 7 122 #define DP_AUX_TIMEOUT_MAX_TRIES 2 123 #define DP_POWER_ON_MAX_TRIES 3 124 125 #define DP_AUX_MAX_BYTES 16 126 127 #define DP_AUX_TIMEOUT_MS 40 128 #define DP_DPCP_RETRY_SLEEP_NS 400 129 130 static const u32 tegra_dp_vs_regs[][4][4] = { 131 /* postcursor2 L0 */ 132 { 133 /* pre-emphasis: L0, L1, L2, L3 */ 134 {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */ 135 {0x1e, 0x25, 0x2d}, /* L1 */ 136 {0x28, 0x32}, /* L2 */ 137 {0x3c}, /* L3 */ 138 }, 139 140 /* postcursor2 L1 */ 141 { 142 {0x12, 0x17, 0x1b, 0x25}, 143 {0x1c, 0x23, 0x2a}, 144 {0x25, 0x2f}, 145 {0x39}, 146 }, 147 148 /* postcursor2 L2 */ 149 { 150 {0x12, 0x16, 0x1a, 0x22}, 151 {0x1b, 0x20, 0x27}, 152 {0x24, 0x2d}, 153 {0x36}, 154 }, 155 156 /* postcursor2 L3 */ 157 { 158 {0x11, 0x14, 0x17, 0x1f}, 159 {0x19, 0x1e, 0x24}, 160 {0x22, 0x2a}, 161 {0x32}, 162 }, 163 }; 164 165 static const u32 tegra_dp_pe_regs[][4][4] = { 166 /* postcursor2 L0 */ 167 { 168 /* pre-emphasis: L0, L1, L2, L3 */ 169 {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */ 170 {0x00, 0x0f, 0x1e}, /* L1 */ 171 {0x00, 0x14}, /* L2 */ 172 {0x00}, /* L3 */ 173 }, 174 175 /* postcursor2 L1 */ 176 { 177 {0x00, 0x0a, 0x14, 0x28}, 178 {0x00, 0x0f, 0x1e}, 179 {0x00, 0x14}, 180 {0x00}, 181 }, 182 183 /* postcursor2 L2 */ 184 { 185 {0x00, 0x0a, 0x14, 0x28}, 186 {0x00, 0x0f, 0x1e}, 187 {0x00, 0x14}, 188 {0x00}, 189 }, 190 191 /* postcursor2 L3 */ 192 { 193 {0x00, 0x0a, 0x14, 0x28}, 194 {0x00, 0x0f, 0x1e}, 195 {0x00, 0x14}, 196 {0x00}, 197 }, 198 }; 199 200 static const u32 tegra_dp_pc_regs[][4][4] = { 201 /* postcursor2 L0 */ 202 { 203 /* pre-emphasis: L0, L1, L2, L3 */ 204 {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */ 205 {0x00, 0x00, 0x00}, /* L1 */ 206 {0x00, 0x00}, /* L2 */ 207 {0x00}, /* L3 */ 208 }, 209 210 /* postcursor2 L1 */ 211 { 212 {0x02, 0x02, 0x04, 0x05}, 213 {0x02, 0x04, 0x05}, 214 {0x04, 0x05}, 215 {0x05}, 216 }, 217 218 /* postcursor2 L2 */ 219 { 220 {0x04, 0x05, 0x08, 0x0b}, 221 {0x05, 0x09, 0x0b}, 222 {0x08, 0x0a}, 223 {0x0b}, 224 }, 225 226 /* postcursor2 L3 */ 227 { 228 {0x05, 0x09, 0x0b, 0x12}, 229 {0x09, 0x0d, 0x12}, 230 {0x0b, 0x0f}, 231 {0x12}, 232 }, 233 }; 234 235 static const u32 tegra_dp_tx_pu[][4][4] = { 236 /* postcursor2 L0 */ 237 { 238 /* pre-emphasis: L0, L1, L2, L3 */ 239 {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */ 240 {0x30, 0x40, 0x60}, /* L1 */ 241 {0x40, 0x60}, /* L2 */ 242 {0x60}, /* L3 */ 243 }, 244 245 /* postcursor2 L1 */ 246 { 247 {0x20, 0x20, 0x30, 0x50}, 248 {0x30, 0x40, 0x50}, 249 {0x40, 0x50}, 250 {0x60}, 251 }, 252 253 /* postcursor2 L2 */ 254 { 255 {0x20, 0x20, 0x30, 0x40}, 256 {0x30, 0x30, 0x40}, 257 {0x40, 0x50}, 258 {0x60}, 259 }, 260 261 /* postcursor2 L3 */ 262 { 263 {0x20, 0x20, 0x20, 0x40}, 264 {0x30, 0x30, 0x40}, 265 {0x40, 0x40}, 266 {0x60}, 267 }, 268 }; 269 270 enum { 271 DRIVECURRENT_LEVEL0 = 0, 272 DRIVECURRENT_LEVEL1 = 1, 273 DRIVECURRENT_LEVEL2 = 2, 274 DRIVECURRENT_LEVEL3 = 3, 275 }; 276 277 enum { 278 PREEMPHASIS_DISABLED = 0, 279 PREEMPHASIS_LEVEL1 = 1, 280 PREEMPHASIS_LEVEL2 = 2, 281 PREEMPHASIS_LEVEL3 = 3, 282 }; 283 284 enum { 285 POSTCURSOR2_LEVEL0 = 0, 286 POSTCURSOR2_LEVEL1 = 1, 287 POSTCURSOR2_LEVEL2 = 2, 288 POSTCURSOR2_LEVEL3 = 3, 289 POSTCURSOR2_SUPPORTED 290 }; 291 292 static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) 293 { 294 return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; 295 } 296 297 static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) 298 { 299 return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; 300 } 301 302 static inline int tegra_dp_is_max_pc(u32 pc) 303 { 304 return (pc < POSTCURSOR2_LEVEL3) ? 0 : 1; 305 } 306 307 /* DPCD definitions which are not defined in drm_dp_helper.h */ 308 #define DP_DPCD_REV_MAJOR_SHIFT 4 309 #define DP_DPCD_REV_MAJOR_MASK (0xf << 4) 310 #define DP_DPCD_REV_MINOR_SHIFT 0 311 #define DP_DPCD_REV_MINOR_MASK 0xf 312 313 #define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6 314 #define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa 315 #define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4 316 317 #define DP_MAX_LANE_COUNT_LANE_1 0x1 318 #define DP_MAX_LANE_COUNT_LANE_2 0x2 319 #define DP_MAX_LANE_COUNT_LANE_4 0x4 320 #define DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (1 << 6) 321 #define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7) 322 323 #define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 324 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) 325 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) 326 #define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 327 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) 328 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5) 329 330 #define DP_MAX_DOWNSPREAD_VAL_NONE 0 331 #define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1 332 #define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6) 333 334 #define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1 335 #define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1) 336 337 #define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7) 338 339 #define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5) 340 #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5) 341 #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5) 342 343 #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0 344 #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1 345 346 #define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f 347 #define NV_DPCD_TRAINING_LANE2_3_SET2 0x110 348 #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2) 349 #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0 << 2) 350 #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6) 351 #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0 << 6) 352 #define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 353 #define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 354 355 #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 356 #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) 357 #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) 358 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 359 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) 360 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) 361 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 362 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) 363 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) 364 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 365 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) 366 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) 367 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 368 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) 369 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) 370 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 371 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) 372 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) 373 374 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) 375 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) 376 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) 377 378 #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 379 #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) 380 #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) 381 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 382 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) 383 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) 384 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 385 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) 386 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) 387 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 388 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) 389 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) 390 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 391 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) 392 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) 393 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 394 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) 395 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) 396 397 #define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 398 #define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3 399 #define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2 400 #define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2) 401 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4 402 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4) 403 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6 404 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6) 405 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) 406 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3 407 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2) 408 409 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) 410 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) 411 #endif 412