1 /* 2 * Copyright (c) 2014, NVIDIA Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _TEGRA_DISPLAYPORT_H 8 #define _TEGRA_DISPLAYPORT_H 9 10 #include <linux/drm_dp_helper.h> 11 12 struct dpaux_ctlr { 13 u32 reserved0; 14 u32 intr_en_aux; 15 u32 reserved2_4; 16 u32 intr_aux; 17 }; 18 19 #define DPAUX_INTR_EN_AUX 0x1 20 #define DPAUX_INTR_AUX 0x5 21 #define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i)) 22 #define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i)) 23 #define DPAUX_DP_AUXADDR 0x29 24 #define DPAUX_DP_AUXCTL 0x2d 25 #define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0 26 #define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff 27 #define DPAUX_DP_AUXCTL_CMD_SHIFT 12 28 #define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) 29 #define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) 30 #define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) 31 #define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) 32 #define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) 33 #define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) 34 #define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) 35 #define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) 36 #define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) 37 #define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16 38 #define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) 39 #define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) 40 #define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) 41 #define DPAUX_DP_AUXCTL_RST_SHIFT 31 42 #define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) 43 #define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) 44 #define DPAUX_DP_AUXSTAT 0x31 45 #define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28 46 #define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) 47 #define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) 48 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20 49 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) 50 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) 51 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) 52 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) 53 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) 54 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) 55 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) 56 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) 57 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) 58 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) 59 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) 60 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) 61 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) 62 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) 63 #define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16 64 #define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) 65 #define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) 66 #define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) 67 #define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) 68 #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) 69 #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) 70 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11 71 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) 72 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) 73 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10 74 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) 75 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) 76 #define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9 77 #define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) 78 #define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) 79 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8 80 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) 81 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) 82 #define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0 83 #define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) 84 #define DPAUX_HPD_CONFIG (0x3d) 85 #define DPAUX_HPD_IRQ_CONFIG 0x41 86 #define DPAUX_DP_AUX_CONFIG 0x45 87 #define DPAUX_HYBRID_PADCTL 0x49 88 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15 89 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) 90 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) 91 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14 92 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) 93 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) 94 #define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12 95 #define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) 96 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) 97 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) 98 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) 99 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) 100 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8 101 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) 102 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) 103 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) 104 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) 105 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) 106 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) 107 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) 108 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) 109 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) 110 #define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2 111 #define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) 112 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1 113 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) 114 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) 115 #define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0 116 #define DPAUX_HYBRID_PADCTL_MODE_AUX 0 117 #define DPAUX_HYBRID_PADCTL_MODE_I2C 1 118 #define DPAUX_HYBRID_SPARE 0x4d 119 #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0 120 #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1 121 122 #define DP_AUX_DEFER_MAX_TRIES 7 123 #define DP_AUX_TIMEOUT_MAX_TRIES 2 124 #define DP_POWER_ON_MAX_TRIES 3 125 126 #define DP_AUX_MAX_BYTES 16 127 128 #define DP_AUX_TIMEOUT_MS 40 129 #define DP_DPCP_RETRY_SLEEP_NS 400 130 131 static const u32 tegra_dp_vs_regs[][4][4] = { 132 /* postcursor2 L0 */ 133 { 134 /* pre-emphasis: L0, L1, L2, L3 */ 135 {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */ 136 {0x1e, 0x25, 0x2d}, /* L1 */ 137 {0x28, 0x32}, /* L2 */ 138 {0x3c}, /* L3 */ 139 }, 140 141 /* postcursor2 L1 */ 142 { 143 {0x12, 0x17, 0x1b, 0x25}, 144 {0x1c, 0x23, 0x2a}, 145 {0x25, 0x2f}, 146 {0x39}, 147 }, 148 149 /* postcursor2 L2 */ 150 { 151 {0x12, 0x16, 0x1a, 0x22}, 152 {0x1b, 0x20, 0x27}, 153 {0x24, 0x2d}, 154 {0x36}, 155 }, 156 157 /* postcursor2 L3 */ 158 { 159 {0x11, 0x14, 0x17, 0x1f}, 160 {0x19, 0x1e, 0x24}, 161 {0x22, 0x2a}, 162 {0x32}, 163 }, 164 }; 165 166 static const u32 tegra_dp_pe_regs[][4][4] = { 167 /* postcursor2 L0 */ 168 { 169 /* pre-emphasis: L0, L1, L2, L3 */ 170 {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */ 171 {0x00, 0x0f, 0x1e}, /* L1 */ 172 {0x00, 0x14}, /* L2 */ 173 {0x00}, /* L3 */ 174 }, 175 176 /* postcursor2 L1 */ 177 { 178 {0x00, 0x0a, 0x14, 0x28}, 179 {0x00, 0x0f, 0x1e}, 180 {0x00, 0x14}, 181 {0x00}, 182 }, 183 184 /* postcursor2 L2 */ 185 { 186 {0x00, 0x0a, 0x14, 0x28}, 187 {0x00, 0x0f, 0x1e}, 188 {0x00, 0x14}, 189 {0x00}, 190 }, 191 192 /* postcursor2 L3 */ 193 { 194 {0x00, 0x0a, 0x14, 0x28}, 195 {0x00, 0x0f, 0x1e}, 196 {0x00, 0x14}, 197 {0x00}, 198 }, 199 }; 200 201 static const u32 tegra_dp_pc_regs[][4][4] = { 202 /* postcursor2 L0 */ 203 { 204 /* pre-emphasis: L0, L1, L2, L3 */ 205 {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */ 206 {0x00, 0x00, 0x00}, /* L1 */ 207 {0x00, 0x00}, /* L2 */ 208 {0x00}, /* L3 */ 209 }, 210 211 /* postcursor2 L1 */ 212 { 213 {0x02, 0x02, 0x04, 0x05}, 214 {0x02, 0x04, 0x05}, 215 {0x04, 0x05}, 216 {0x05}, 217 }, 218 219 /* postcursor2 L2 */ 220 { 221 {0x04, 0x05, 0x08, 0x0b}, 222 {0x05, 0x09, 0x0b}, 223 {0x08, 0x0a}, 224 {0x0b}, 225 }, 226 227 /* postcursor2 L3 */ 228 { 229 {0x05, 0x09, 0x0b, 0x12}, 230 {0x09, 0x0d, 0x12}, 231 {0x0b, 0x0f}, 232 {0x12}, 233 }, 234 }; 235 236 static const u32 tegra_dp_tx_pu[][4][4] = { 237 /* postcursor2 L0 */ 238 { 239 /* pre-emphasis: L0, L1, L2, L3 */ 240 {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */ 241 {0x30, 0x40, 0x60}, /* L1 */ 242 {0x40, 0x60}, /* L2 */ 243 {0x60}, /* L3 */ 244 }, 245 246 /* postcursor2 L1 */ 247 { 248 {0x20, 0x20, 0x30, 0x50}, 249 {0x30, 0x40, 0x50}, 250 {0x40, 0x50}, 251 {0x60}, 252 }, 253 254 /* postcursor2 L2 */ 255 { 256 {0x20, 0x20, 0x30, 0x40}, 257 {0x30, 0x30, 0x40}, 258 {0x40, 0x50}, 259 {0x60}, 260 }, 261 262 /* postcursor2 L3 */ 263 { 264 {0x20, 0x20, 0x20, 0x40}, 265 {0x30, 0x30, 0x40}, 266 {0x40, 0x40}, 267 {0x60}, 268 }, 269 }; 270 271 enum { 272 DRIVECURRENT_LEVEL0 = 0, 273 DRIVECURRENT_LEVEL1 = 1, 274 DRIVECURRENT_LEVEL2 = 2, 275 DRIVECURRENT_LEVEL3 = 3, 276 }; 277 278 enum { 279 PREEMPHASIS_DISABLED = 0, 280 PREEMPHASIS_LEVEL1 = 1, 281 PREEMPHASIS_LEVEL2 = 2, 282 PREEMPHASIS_LEVEL3 = 3, 283 }; 284 285 enum { 286 POSTCURSOR2_LEVEL0 = 0, 287 POSTCURSOR2_LEVEL1 = 1, 288 POSTCURSOR2_LEVEL2 = 2, 289 POSTCURSOR2_LEVEL3 = 3, 290 POSTCURSOR2_SUPPORTED 291 }; 292 293 static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) 294 { 295 return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; 296 } 297 298 static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) 299 { 300 return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; 301 } 302 303 static inline int tegra_dp_is_max_pc(u32 pc) 304 { 305 return (pc < POSTCURSOR2_LEVEL3) ? 0 : 1; 306 } 307 308 /* DPCD definitions which are not defined in drm_dp_helper.h */ 309 #define DP_DPCD_REV_MAJOR_SHIFT 4 310 #define DP_DPCD_REV_MAJOR_MASK (0xf << 4) 311 #define DP_DPCD_REV_MINOR_SHIFT 0 312 #define DP_DPCD_REV_MINOR_MASK 0xf 313 314 #define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6 315 #define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa 316 #define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4 317 318 #define DP_MAX_LANE_COUNT_LANE_1 0x1 319 #define DP_MAX_LANE_COUNT_LANE_2 0x2 320 #define DP_MAX_LANE_COUNT_LANE_4 0x4 321 #define DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (1 << 6) 322 #define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7) 323 324 #define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 325 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) 326 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) 327 #define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 328 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) 329 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5) 330 331 #define DP_MAX_DOWNSPREAD_VAL_NONE 0 332 #define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1 333 #define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6) 334 335 #define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1 336 #define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1) 337 338 #define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7) 339 340 #define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5) 341 #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5) 342 #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5) 343 344 #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0 345 #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1 346 347 #define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f 348 #define NV_DPCD_TRAINING_LANE2_3_SET2 0x110 349 #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2) 350 #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0 << 2) 351 #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6) 352 #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0 << 6) 353 #define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 354 #define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 355 356 #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 357 #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) 358 #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) 359 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 360 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) 361 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) 362 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 363 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) 364 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) 365 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 366 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) 367 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) 368 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 369 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) 370 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) 371 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 372 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) 373 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) 374 375 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) 376 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) 377 #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) 378 379 #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 380 #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) 381 #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) 382 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 383 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) 384 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) 385 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 386 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) 387 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) 388 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 389 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) 390 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) 391 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 392 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) 393 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) 394 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 395 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) 396 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) 397 398 #define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 399 #define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3 400 #define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2 401 #define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2) 402 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4 403 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4) 404 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6 405 #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6) 406 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) 407 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3 408 #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2) 409 410 #define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) 411 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) 412 #endif 413