1 /* 2 * Copyright 2014 Google Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Extracted from Chromium coreboot commit 3f59b13d 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <edid.h> 12 #include <errno.h> 13 #include <displayport.h> 14 #include <edid.h> 15 #include <fdtdec.h> 16 #include <lcd.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/pwm.h> 21 #include <asm/arch-tegra/dc.h> 22 #include "displayport.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* return in 1000ths of a Hertz */ 27 static int tegra_dc_calc_refresh(const struct display_timing *timing) 28 { 29 int h_total, v_total, refresh; 30 int pclk = timing->pixelclock.typ; 31 32 h_total = timing->hactive.typ + timing->hfront_porch.typ + 33 timing->hback_porch.typ + timing->hsync_len.typ; 34 v_total = timing->vactive.typ + timing->vfront_porch.typ + 35 timing->vback_porch.typ + timing->vsync_len.typ; 36 if (!pclk || !h_total || !v_total) 37 return 0; 38 refresh = pclk / h_total; 39 refresh *= 1000; 40 refresh /= v_total; 41 42 return refresh; 43 } 44 45 static void print_mode(const struct display_timing *timing) 46 { 47 int refresh = tegra_dc_calc_refresh(timing); 48 49 debug("MODE:%dx%d@%d.%03uHz pclk=%d\n", 50 timing->hactive.typ, timing->vactive.typ, refresh / 1000, 51 refresh % 1000, timing->pixelclock.typ); 52 } 53 54 static int update_display_mode(struct dc_ctlr *disp_ctrl, 55 const struct display_timing *timing, 56 int href_to_sync, int vref_to_sync) 57 { 58 print_mode(timing); 59 60 writel(0x1, &disp_ctrl->disp.disp_timing_opt); 61 62 writel(vref_to_sync << 16 | href_to_sync, 63 &disp_ctrl->disp.ref_to_sync); 64 65 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, 66 &disp_ctrl->disp.sync_width); 67 68 writel(((timing->vback_porch.typ - vref_to_sync) << 16) | 69 timing->hback_porch.typ, &disp_ctrl->disp.back_porch); 70 71 writel(((timing->vfront_porch.typ + vref_to_sync) << 16) | 72 timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); 73 74 writel(timing->hactive.typ | (timing->vactive.typ << 16), 75 &disp_ctrl->disp.disp_active); 76 77 /** 78 * We want to use PLLD_out0, which is PLLD / 2: 79 * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. 80 * 81 * Currently most panels work inside clock range 50MHz~100MHz, and PLLD 82 * has some requirements to have VCO in range 500MHz~1000MHz (see 83 * clock.c for more detail). To simplify calculation, we set 84 * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values 85 * may be calculated by clock_display, to allow wider frequency range. 86 * 87 * Note ShiftClockDiv is a 7.1 format value. 88 */ 89 const u32 shift_clock_div = 1; 90 writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | 91 ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, 92 &disp_ctrl->disp.disp_clk_ctrl); 93 debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__, 94 timing->pixelclock.typ, shift_clock_div); 95 return 0; 96 } 97 98 static u32 tegra_dc_poll_register(void *reg, 99 u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) 100 { 101 u32 temp = timeout_us; 102 u32 reg_val = 0; 103 104 do { 105 udelay(poll_interval_us); 106 reg_val = readl(reg); 107 if (timeout_us > poll_interval_us) 108 timeout_us -= poll_interval_us; 109 else 110 break; 111 } while ((reg_val & mask) != exp_val); 112 113 if ((reg_val & mask) == exp_val) 114 return 0; /* success */ 115 116 return temp; 117 } 118 119 int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl) 120 { 121 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); 122 123 if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl, 124 GENERAL_ACT_REQ, 0, 100, 125 DC_POLL_TIMEOUT_MS * 1000)) { 126 debug("dc timeout waiting for DC to stop\n"); 127 return -ETIMEDOUT; 128 } 129 130 return 0; 131 } 132 133 static struct display_timing min_mode = { 134 .hsync_len = { .typ = 1 }, 135 .vsync_len = { .typ = 1 }, 136 .hback_porch = { .typ = 20 }, 137 .vback_porch = { .typ = 0 }, 138 .hactive = { .typ = 16 }, 139 .vactive = { .typ = 16 }, 140 .hfront_porch = { .typ = 1 }, 141 .vfront_porch = { .typ = 2 }, 142 }; 143 144 /* Disable windows and set minimum raster timings */ 145 void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, 146 int *dc_reg_ctx) 147 { 148 const int href_to_sync = 0, vref_to_sync = 1; 149 int selected_windows, i; 150 151 selected_windows = readl(&disp_ctrl->cmd.disp_win_header); 152 153 /* Store and clear window options */ 154 for (i = 0; i < DC_N_WINDOWS; ++i) { 155 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); 156 dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt); 157 writel(0, &disp_ctrl->win.win_opt); 158 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); 159 } 160 161 writel(selected_windows, &disp_ctrl->cmd.disp_win_header); 162 163 /* Store current raster timings and set minimum timings */ 164 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync); 165 writel(href_to_sync | (vref_to_sync << 16), 166 &disp_ctrl->disp.ref_to_sync); 167 168 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width); 169 writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16), 170 &disp_ctrl->disp.sync_width); 171 172 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch); 173 writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16), 174 &disp_ctrl->disp.back_porch); 175 176 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch); 177 writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16), 178 &disp_ctrl->disp.front_porch); 179 180 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active); 181 writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16), 182 &disp_ctrl->disp.disp_active); 183 184 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); 185 } 186 187 /* Restore previous windows status and raster timings */ 188 void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, 189 int *dc_reg_ctx) 190 { 191 int selected_windows, i; 192 193 selected_windows = readl(&disp_ctrl->cmd.disp_win_header); 194 195 for (i = 0; i < DC_N_WINDOWS; ++i) { 196 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); 197 writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt); 198 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); 199 } 200 201 writel(selected_windows, &disp_ctrl->cmd.disp_win_header); 202 203 writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync); 204 writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width); 205 writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch); 206 writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch); 207 writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active); 208 209 writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl); 210 } 211 212 static int tegra_depth_for_bpp(int bpp) 213 { 214 switch (bpp) { 215 case 32: 216 return COLOR_DEPTH_R8G8B8A8; 217 case 16: 218 return COLOR_DEPTH_B5G6R5; 219 default: 220 debug("Unsupported LCD bit depth"); 221 return -1; 222 } 223 } 224 225 static int update_window(struct dc_ctlr *disp_ctrl, 226 u32 frame_buffer, int fb_bits_per_pixel, 227 const struct display_timing *timing) 228 { 229 const u32 colour_white = 0xffffff; 230 int colour_depth; 231 u32 val; 232 233 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); 234 235 writel(((timing->vactive.typ << 16) | timing->hactive.typ), 236 &disp_ctrl->win.size); 237 writel(((timing->vactive.typ << 16) | 238 (timing->hactive.typ * fb_bits_per_pixel / 8)), 239 &disp_ctrl->win.prescaled_size); 240 writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) / 241 32 * 32), &disp_ctrl->win.line_stride); 242 243 colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel); 244 if (colour_depth == -1) 245 return -EINVAL; 246 247 writel(colour_depth, &disp_ctrl->win.color_depth); 248 249 writel(frame_buffer, &disp_ctrl->winbuf.start_addr); 250 writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT, 251 &disp_ctrl->win.dda_increment); 252 253 writel(colour_white, &disp_ctrl->disp.blend_background_color); 254 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, 255 &disp_ctrl->cmd.disp_cmd); 256 257 writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); 258 259 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 260 val |= GENERAL_UPDATE | WIN_A_UPDATE; 261 writel(val, &disp_ctrl->cmd.state_ctrl); 262 263 /* Enable win_a */ 264 val = readl(&disp_ctrl->win.win_opt); 265 writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt); 266 267 return 0; 268 } 269 270 static int tegra_dc_init(struct dc_ctlr *disp_ctrl) 271 { 272 /* do not accept interrupts during initialization */ 273 writel(0x00000000, &disp_ctrl->cmd.int_mask); 274 writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, 275 &disp_ctrl->cmd.state_access); 276 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); 277 writel(0x00000000, &disp_ctrl->win.win_opt); 278 writel(0x00000000, &disp_ctrl->win.byte_swap); 279 writel(0x00000000, &disp_ctrl->win.buffer_ctrl); 280 281 writel(0x00000000, &disp_ctrl->win.pos); 282 writel(0x00000000, &disp_ctrl->win.h_initial_dda); 283 writel(0x00000000, &disp_ctrl->win.v_initial_dda); 284 writel(0x00000000, &disp_ctrl->win.dda_increment); 285 writel(0x00000000, &disp_ctrl->win.dv_ctrl); 286 287 writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl); 288 writel(0x00000000, &disp_ctrl->win.blend_match_select); 289 writel(0x00000000, &disp_ctrl->win.blend_nomatch_select); 290 writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit); 291 292 writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi); 293 writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset); 294 writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset); 295 296 writel(0x00000000, &disp_ctrl->com.crc_checksum); 297 writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]); 298 writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]); 299 writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]); 300 writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]); 301 writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0); 302 303 return 0; 304 } 305 306 static void dump_config(int panel_bpp, struct display_timing *timing) 307 { 308 printf("timing->hactive.typ = %d\n", timing->hactive.typ); 309 printf("timing->vactive.typ = %d\n", timing->vactive.typ); 310 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); 311 312 printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ); 313 printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ); 314 printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ); 315 316 printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ); 317 printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ); 318 printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ); 319 320 printf("panel_bits_per_pixel = %d\n", panel_bpp); 321 } 322 323 static int display_update_config_from_edid(struct udevice *dp_dev, 324 int *panel_bppp, 325 struct display_timing *timing) 326 { 327 u8 buf[EDID_SIZE]; 328 int bpc, ret; 329 330 ret = display_port_read_edid(dp_dev, buf, sizeof(buf)); 331 if (ret < 0) 332 return ret; 333 ret = edid_get_timing(buf, ret, timing, &bpc); 334 if (ret) 335 return ret; 336 337 /* Use this information if valid */ 338 if (bpc != -1) 339 *panel_bppp = bpc * 3; 340 341 return 0; 342 } 343 344 /* Somewhat torturous method */ 345 static int get_backlight_info(const void *blob, struct gpio_desc *vdd, 346 struct gpio_desc *enable, int *pwmp) 347 { 348 int sor, panel, backlight, power; 349 const u32 *prop; 350 int len; 351 int ret; 352 353 *pwmp = 0; 354 sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); 355 if (sor < 0) 356 return -ENOENT; 357 panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel"); 358 if (panel < 0) 359 return -ENOENT; 360 backlight = fdtdec_lookup_phandle(blob, panel, "backlight"); 361 if (backlight < 0) 362 return -ENOENT; 363 ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0, 364 enable, GPIOD_IS_OUT); 365 if (ret) 366 return ret; 367 prop = fdt_getprop(blob, backlight, "pwms", &len); 368 if (!prop || len != 3 * sizeof(u32)) 369 return -EINVAL; 370 *pwmp = fdt32_to_cpu(prop[1]); 371 372 power = fdtdec_lookup_phandle(blob, backlight, "power-supply"); 373 if (power < 0) 374 return -ENOENT; 375 ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd, 376 GPIOD_IS_OUT); 377 if (ret) 378 goto err; 379 380 return 0; 381 382 err: 383 dm_gpio_free(NULL, enable); 384 return ret; 385 } 386 387 int display_init(void *lcdbase, int fb_bits_per_pixel, 388 struct display_timing *timing) 389 { 390 struct dc_ctlr *dc_ctlr; 391 const void *blob = gd->fdt_blob; 392 struct udevice *dp_dev; 393 const int href_to_sync = 1, vref_to_sync = 1; 394 int panel_bpp = 18; /* default 18 bits per pixel */ 395 u32 plld_rate; 396 struct gpio_desc vdd_gpio, enable_gpio; 397 int pwm; 398 int node; 399 int ret; 400 401 ret = uclass_get_device(UCLASS_DISPLAY_PORT, 0, &dp_dev); 402 if (ret) 403 return ret; 404 405 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); 406 if (node < 0) 407 return -ENOENT; 408 dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); 409 if (fdtdec_decode_display_timing(blob, node, 0, timing)) 410 return -EINVAL; 411 412 ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); 413 if (ret) { 414 debug("%s: Failed to decode EDID, using defaults\n", __func__); 415 dump_config(panel_bpp, timing); 416 } 417 418 if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { 419 dm_gpio_set_value(&vdd_gpio, 1); 420 debug("%s: backlight vdd setting gpio %08x to %d\n", 421 __func__, gpio_get_number(&vdd_gpio), 1); 422 } 423 424 /* 425 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER 426 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the 427 * update_display_mode() for detail. 428 */ 429 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); 430 if (plld_rate == 0) { 431 printf("dc: clock init failed\n"); 432 return -EIO; 433 } else if (plld_rate != timing->pixelclock.typ * 2) { 434 debug("dc: plld rounded to %u\n", plld_rate); 435 timing->pixelclock.typ = plld_rate / 2; 436 } 437 438 /* Init dc */ 439 ret = tegra_dc_init(dc_ctlr); 440 if (ret) { 441 debug("dc: init failed\n"); 442 return ret; 443 } 444 445 /* Configure dc mode */ 446 ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); 447 if (ret) { 448 debug("dc: failed to configure display mode\n"); 449 return ret; 450 } 451 452 /* Enable dp */ 453 ret = display_port_enable(dp_dev, panel_bpp, timing); 454 if (ret) 455 return ret; 456 457 ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); 458 if (ret) 459 return ret; 460 461 /* Set up Tegra PWM to drive the panel backlight */ 462 pwm_enable(pwm, 0, 220, 0x2e); 463 udelay(10 * 1000); 464 465 if (dm_gpio_is_valid(&enable_gpio)) { 466 dm_gpio_set_value(&enable_gpio, 1); 467 debug("%s: backlight enable setting gpio %08x to %d\n", 468 __func__, gpio_get_number(&enable_gpio), 1); 469 } 470 471 return 0; 472 } 473