1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Google Inc.
4  *
5  * Extracted from Chromium coreboot commit 3f59b13d
6  */
7 
8 #include <common.h>
9 #include <dm.h>
10 #include <edid.h>
11 #include <errno.h>
12 #include <display.h>
13 #include <edid.h>
14 #include <lcd.h>
15 #include <video.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/pwm.h>
20 #include <asm/arch-tegra/dc.h>
21 #include <dm/uclass-internal.h>
22 #include "displayport.h"
23 
24 /* return in 1000ths of a Hertz */
25 static int tegra_dc_calc_refresh(const struct display_timing *timing)
26 {
27 	int h_total, v_total, refresh;
28 	int pclk = timing->pixelclock.typ;
29 
30 	h_total = timing->hactive.typ + timing->hfront_porch.typ +
31 			timing->hback_porch.typ + timing->hsync_len.typ;
32 	v_total = timing->vactive.typ + timing->vfront_porch.typ +
33 			timing->vback_porch.typ + timing->vsync_len.typ;
34 	if (!pclk || !h_total || !v_total)
35 		return 0;
36 	refresh = pclk / h_total;
37 	refresh *= 1000;
38 	refresh /= v_total;
39 
40 	return refresh;
41 }
42 
43 static void print_mode(const struct display_timing *timing)
44 {
45 	int refresh = tegra_dc_calc_refresh(timing);
46 
47 	debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
48 	      timing->hactive.typ, timing->vactive.typ, refresh / 1000,
49 	      refresh % 1000, timing->pixelclock.typ);
50 }
51 
52 static int update_display_mode(struct dc_ctlr *disp_ctrl,
53 			       const struct display_timing *timing,
54 			       int href_to_sync, int vref_to_sync)
55 {
56 	print_mode(timing);
57 
58 	writel(0x1, &disp_ctrl->disp.disp_timing_opt);
59 
60 	writel(vref_to_sync << 16 | href_to_sync,
61 	       &disp_ctrl->disp.ref_to_sync);
62 
63 	writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
64 	       &disp_ctrl->disp.sync_width);
65 
66 	writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
67 		timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
68 
69 	writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
70 		timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
71 
72 	writel(timing->hactive.typ | (timing->vactive.typ << 16),
73 	       &disp_ctrl->disp.disp_active);
74 
75 	/**
76 	 * We want to use PLLD_out0, which is PLLD / 2:
77 	 *   PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
78 	 *
79 	 * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
80 	 * has some requirements to have VCO in range 500MHz~1000MHz (see
81 	 * clock.c for more detail). To simplify calculation, we set
82 	 * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
83 	 * may be calculated by clock_display, to allow wider frequency range.
84 	 *
85 	 * Note ShiftClockDiv is a 7.1 format value.
86 	 */
87 	const u32 shift_clock_div = 1;
88 	writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
89 	       ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
90 	       &disp_ctrl->disp.disp_clk_ctrl);
91 	debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
92 	      timing->pixelclock.typ, shift_clock_div);
93 	return 0;
94 }
95 
96 static u32 tegra_dc_poll_register(void *reg,
97 	u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
98 {
99 	u32 temp = timeout_us;
100 	u32 reg_val = 0;
101 
102 	do {
103 		udelay(poll_interval_us);
104 		reg_val = readl(reg);
105 		if (timeout_us > poll_interval_us)
106 			timeout_us -= poll_interval_us;
107 		else
108 			break;
109 	} while ((reg_val & mask) != exp_val);
110 
111 	if ((reg_val & mask) == exp_val)
112 		return 0;	/* success */
113 
114 	return temp;
115 }
116 
117 int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
118 {
119 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
120 
121 	if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
122 				   GENERAL_ACT_REQ, 0, 100,
123 				   DC_POLL_TIMEOUT_MS * 1000)) {
124 		debug("dc timeout waiting for DC to stop\n");
125 		return -ETIMEDOUT;
126 	}
127 
128 	return 0;
129 }
130 
131 static struct display_timing min_mode = {
132 	.hsync_len = { .typ = 1 },
133 	.vsync_len = { .typ = 1 },
134 	.hback_porch = { .typ = 20 },
135 	.vback_porch = { .typ = 0 },
136 	.hactive = { .typ = 16 },
137 	.vactive = { .typ = 16 },
138 	.hfront_porch = { .typ = 1 },
139 	.vfront_porch = { .typ = 2 },
140 };
141 
142 /* Disable windows and set minimum raster timings */
143 void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
144 					   int *dc_reg_ctx)
145 {
146 	const int href_to_sync = 0, vref_to_sync = 1;
147 	int selected_windows, i;
148 
149 	selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
150 
151 	/* Store and clear window options */
152 	for (i = 0; i < DC_N_WINDOWS; ++i) {
153 		writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
154 		dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
155 		writel(0, &disp_ctrl->win.win_opt);
156 		writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
157 	}
158 
159 	writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
160 
161 	/* Store current raster timings and set minimum timings */
162 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
163 	writel(href_to_sync | (vref_to_sync << 16),
164 	       &disp_ctrl->disp.ref_to_sync);
165 
166 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
167 	writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
168 	       &disp_ctrl->disp.sync_width);
169 
170 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
171 	writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
172 	       &disp_ctrl->disp.back_porch);
173 
174 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
175 	writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
176 	       &disp_ctrl->disp.front_porch);
177 
178 	dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
179 	writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
180 	       &disp_ctrl->disp.disp_active);
181 
182 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
183 }
184 
185 /* Restore previous windows status and raster timings */
186 void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
187 					 int *dc_reg_ctx)
188 {
189 	int selected_windows, i;
190 
191 	selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
192 
193 	for (i = 0; i < DC_N_WINDOWS; ++i) {
194 		writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
195 		writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
196 		writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
197 	}
198 
199 	writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
200 
201 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
202 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
203 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
204 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
205 	writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
206 
207 	writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
208 }
209 
210 static int tegra_depth_for_bpp(int bpp)
211 {
212 	switch (bpp) {
213 	case 32:
214 		return COLOR_DEPTH_R8G8B8A8;
215 	case 16:
216 		return COLOR_DEPTH_B5G6R5;
217 	default:
218 		debug("Unsupported LCD bit depth");
219 		return -1;
220 	}
221 }
222 
223 static int update_window(struct dc_ctlr *disp_ctrl,
224 			 u32 frame_buffer, int fb_bits_per_pixel,
225 			 const struct display_timing *timing)
226 {
227 	const u32 colour_white = 0xffffff;
228 	int colour_depth;
229 	u32 val;
230 
231 	writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
232 
233 	writel(((timing->vactive.typ << 16) | timing->hactive.typ),
234 	       &disp_ctrl->win.size);
235 	writel(((timing->vactive.typ << 16) |
236 		(timing->hactive.typ * fb_bits_per_pixel / 8)),
237 		&disp_ctrl->win.prescaled_size);
238 	writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
239 		32 * 32), &disp_ctrl->win.line_stride);
240 
241 	colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
242 	if (colour_depth == -1)
243 		return -EINVAL;
244 
245 	writel(colour_depth, &disp_ctrl->win.color_depth);
246 
247 	writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
248 	writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
249 	       &disp_ctrl->win.dda_increment);
250 
251 	writel(colour_white, &disp_ctrl->disp.blend_background_color);
252 	writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
253 	       &disp_ctrl->cmd.disp_cmd);
254 
255 	writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
256 
257 	val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
258 	val |= GENERAL_UPDATE | WIN_A_UPDATE;
259 	writel(val, &disp_ctrl->cmd.state_ctrl);
260 
261 	/* Enable win_a */
262 	val = readl(&disp_ctrl->win.win_opt);
263 	writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
264 
265 	return 0;
266 }
267 
268 static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
269 {
270 	/* do not accept interrupts during initialization */
271 	writel(0x00000000, &disp_ctrl->cmd.int_mask);
272 	writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
273 	       &disp_ctrl->cmd.state_access);
274 	writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
275 	writel(0x00000000, &disp_ctrl->win.win_opt);
276 	writel(0x00000000, &disp_ctrl->win.byte_swap);
277 	writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
278 
279 	writel(0x00000000, &disp_ctrl->win.pos);
280 	writel(0x00000000, &disp_ctrl->win.h_initial_dda);
281 	writel(0x00000000, &disp_ctrl->win.v_initial_dda);
282 	writel(0x00000000, &disp_ctrl->win.dda_increment);
283 	writel(0x00000000, &disp_ctrl->win.dv_ctrl);
284 
285 	writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
286 	writel(0x00000000, &disp_ctrl->win.blend_match_select);
287 	writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
288 	writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
289 
290 	writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
291 	writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
292 	writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
293 
294 	writel(0x00000000, &disp_ctrl->com.crc_checksum);
295 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
296 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
297 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
298 	writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
299 	writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
300 
301 	return 0;
302 }
303 
304 static void dump_config(int panel_bpp, struct display_timing *timing)
305 {
306 	printf("timing->hactive.typ = %d\n", timing->hactive.typ);
307 	printf("timing->vactive.typ = %d\n", timing->vactive.typ);
308 	printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
309 
310 	printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
311 	printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
312 	printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
313 
314 	printf("timing->vfront_porch.typ  %d\n", timing->vfront_porch.typ);
315 	printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
316 	printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
317 
318 	printf("panel_bits_per_pixel = %d\n", panel_bpp);
319 }
320 
321 static int display_update_config_from_edid(struct udevice *dp_dev,
322 					   int *panel_bppp,
323 					   struct display_timing *timing)
324 {
325 	return display_read_timing(dp_dev, timing);
326 }
327 
328 static int display_init(struct udevice *dev, void *lcdbase,
329 			int fb_bits_per_pixel, struct display_timing *timing)
330 {
331 	struct display_plat *disp_uc_plat;
332 	struct dc_ctlr *dc_ctlr;
333 	struct udevice *dp_dev;
334 	const int href_to_sync = 1, vref_to_sync = 1;
335 	int panel_bpp = 18;	/* default 18 bits per pixel */
336 	u32 plld_rate;
337 	int ret;
338 
339 	/*
340 	 * Before we probe the display device (eDP), tell it that this device
341 	 * is the source of the display data.
342 	 */
343 	ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
344 	if (ret) {
345 		debug("%s: device '%s' display not found (ret=%d)\n", __func__,
346 		      dev->name, ret);
347 		return ret;
348 	}
349 
350 	disp_uc_plat = dev_get_uclass_platdata(dp_dev);
351 	debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
352 	      disp_uc_plat);
353 	disp_uc_plat->src_dev = dev;
354 
355 	ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
356 	if (ret) {
357 		debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
358 		return ret;
359 	}
360 
361 	dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
362 	if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
363 		debug("%s: Failed to decode display timing\n", __func__);
364 		return -EINVAL;
365 	}
366 
367 	ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
368 	if (ret) {
369 		debug("%s: Failed to decode EDID, using defaults\n", __func__);
370 		dump_config(panel_bpp, timing);
371 	}
372 
373 	/*
374 	 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
375 	 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
376 	 * update_display_mode() for detail.
377 	 */
378 	plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
379 	if (plld_rate == 0) {
380 		printf("dc: clock init failed\n");
381 		return -EIO;
382 	} else if (plld_rate != timing->pixelclock.typ * 2) {
383 		debug("dc: plld rounded to %u\n", plld_rate);
384 		timing->pixelclock.typ = plld_rate / 2;
385 	}
386 
387 	/* Init dc */
388 	ret = tegra_dc_init(dc_ctlr);
389 	if (ret) {
390 		debug("dc: init failed\n");
391 		return ret;
392 	}
393 
394 	/* Configure dc mode */
395 	ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
396 	if (ret) {
397 		debug("dc: failed to configure display mode\n");
398 		return ret;
399 	}
400 
401 	/* Enable dp */
402 	ret = display_enable(dp_dev, panel_bpp, timing);
403 	if (ret) {
404 		debug("dc: failed to enable display: ret=%d\n", ret);
405 		return ret;
406 	}
407 
408 	ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
409 	if (ret) {
410 		debug("dc: failed to update window\n");
411 		return ret;
412 	}
413 	debug("%s: ready\n", __func__);
414 
415 	return 0;
416 }
417 
418 enum {
419 	/* Maximum LCD size we support */
420 	LCD_MAX_WIDTH		= 1920,
421 	LCD_MAX_HEIGHT		= 1200,
422 	LCD_MAX_LOG2_BPP	= 4,		/* 2^4 = 16 bpp */
423 };
424 
425 static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
426 			     enum video_log2_bpp l2bpp)
427 {
428 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
429 	struct display_timing timing;
430 	int ret;
431 
432 	clock_set_up_plldp();
433 	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
434 
435 	clock_enable(PERIPH_ID_HOST1X);
436 	clock_enable(PERIPH_ID_DISP1);
437 	clock_enable(PERIPH_ID_PWM);
438 	clock_enable(PERIPH_ID_DPAUX);
439 	clock_enable(PERIPH_ID_SOR0);
440 	udelay(2);
441 
442 	reset_set_enable(PERIPH_ID_HOST1X, 0);
443 	reset_set_enable(PERIPH_ID_DISP1, 0);
444 	reset_set_enable(PERIPH_ID_PWM, 0);
445 	reset_set_enable(PERIPH_ID_DPAUX, 0);
446 	reset_set_enable(PERIPH_ID_SOR0, 0);
447 
448 	ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
449 	if (ret)
450 		return ret;
451 
452 	uc_priv->xsize = roundup(timing.hactive.typ, 16);
453 	uc_priv->ysize = timing.vactive.typ;
454 	uc_priv->bpix = l2bpp;
455 
456 	video_set_flush_dcache(dev, 1);
457 	debug("%s: done\n", __func__);
458 
459 	return 0;
460 }
461 
462 static int tegra124_lcd_probe(struct udevice *dev)
463 {
464 	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
465 	ulong start;
466 	int ret;
467 
468 	start = get_timer(0);
469 	bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
470 	ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
471 	bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
472 	debug("LCD init took %lu ms\n", get_timer(start));
473 	if (ret)
474 		printf("%s: Error %d\n", __func__, ret);
475 
476 	return 0;
477 }
478 
479 static int tegra124_lcd_bind(struct udevice *dev)
480 {
481 	struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
482 
483 	uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
484 			(1 << VIDEO_BPP16) / 8;
485 	debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
486 
487 	return 0;
488 }
489 
490 static const struct udevice_id tegra124_lcd_ids[] = {
491 	{ .compatible = "nvidia,tegra124-dc" },
492 	{ }
493 };
494 
495 U_BOOT_DRIVER(tegra124_dc) = {
496 	.name	= "tegra124-dc",
497 	.id	= UCLASS_VIDEO,
498 	.of_match = tegra124_lcd_ids,
499 	.bind	= tegra124_lcd_bind,
500 	.probe	= tegra124_lcd_probe,
501 };
502