1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk> 4 * 5 * Based on the Linux driver, (C) 2012 Texas Instruments 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <display.h> 11 #include <i2c.h> 12 13 /* 14 * TDA19988 uses paged registers. We encode the page# in the upper 15 * bits of the register#. It also means that reads/writes to a register 16 * have to ensure that the register's page is selected as the current 17 * page. 18 */ 19 #define REG(page, addr) (((page) << 8) | (addr)) 20 #define REG2ADDR(reg) ((reg) & 0xff) 21 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 22 23 /* register for setting current page */ 24 #define REG_CURRENT_PAGE 0xff 25 26 /* Page 00h: General Control */ 27 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 28 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 29 #define MAIN_CNTRL0_SR BIT(0) 30 #define MAIN_CNTRL0_DECS BIT(1) 31 #define MAIN_CNTRL0_DEHS BIT(2) 32 #define MAIN_CNTRL0_CECS BIT(3) 33 #define MAIN_CNTRL0_CEHS BIT(4) 34 #define MAIN_CNTRL0_SCALER BIT(7) 35 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 36 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 37 #define SOFTRESET_AUDIO BIT(0) 38 #define SOFTRESET_I2C_MASTER BIT(1) 39 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 40 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 41 #define I2C_MASTER_DIS_MM BIT(0) 42 #define I2C_MASTER_DIS_FILT BIT(1) 43 #define I2C_MASTER_APP_STRT_LAT BIT(2) 44 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 45 #define FEAT_POWERDOWN_PREFILT BIT(0) 46 #define FEAT_POWERDOWN_CSC BIT(1) 47 #define FEAT_POWERDOWN_SPDIF BIT(3) 48 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 49 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 50 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 51 #define INT_FLAGS_2_EDID_BLK_RD BIT(1) 52 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 53 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 54 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 55 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 56 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 57 #define VIP_CNTRL_0_MIRR_A BIT(7) 58 #define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 59 #define VIP_CNTRL_0_MIRR_B BIT(3) 60 #define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 61 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 62 #define VIP_CNTRL_1_MIRR_C BIT(7) 63 #define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 64 #define VIP_CNTRL_1_MIRR_D BIT(3) 65 #define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 66 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 67 #define VIP_CNTRL_2_MIRR_E BIT(7) 68 #define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 69 #define VIP_CNTRL_2_MIRR_F BIT(3) 70 #define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 71 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 72 #define VIP_CNTRL_3_X_TGL BIT(0) 73 #define VIP_CNTRL_3_H_TGL BIT(1) 74 #define VIP_CNTRL_3_V_TGL BIT(2) 75 #define VIP_CNTRL_3_EMB BIT(3) 76 #define VIP_CNTRL_3_SYNC_DE BIT(4) 77 #define VIP_CNTRL_3_SYNC_HS BIT(5) 78 #define VIP_CNTRL_3_DE_INT BIT(6) 79 #define VIP_CNTRL_3_EDGE BIT(7) 80 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 81 #define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 82 #define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 83 #define VIP_CNTRL_4_CCIR656 BIT(4) 84 #define VIP_CNTRL_4_656_ALT BIT(5) 85 #define VIP_CNTRL_4_TST_656 BIT(6) 86 #define VIP_CNTRL_4_TST_PAT BIT(7) 87 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 88 #define VIP_CNTRL_5_CKCASE BIT(0) 89 #define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 90 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 91 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 92 #define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 93 #define MAT_CONTRL_MAT_BP BIT(2) 94 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 95 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 96 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 97 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 98 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 99 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 100 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 101 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 102 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 103 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 104 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 105 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 106 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 107 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 108 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 109 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 110 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 111 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 112 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 113 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 114 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 115 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 116 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 117 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 118 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 119 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 120 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 121 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 122 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 123 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 124 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 125 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 126 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 127 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 128 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 129 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 130 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 131 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 132 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 133 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 134 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 135 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 136 #define TBG_CNTRL_0_TOP_TGL BIT(0) 137 #define TBG_CNTRL_0_TOP_SEL BIT(1) 138 #define TBG_CNTRL_0_DE_EXT BIT(2) 139 #define TBG_CNTRL_0_TOP_EXT BIT(3) 140 #define TBG_CNTRL_0_FRAME_DIS BIT(5) 141 #define TBG_CNTRL_0_SYNC_MTHD BIT(6) 142 #define TBG_CNTRL_0_SYNC_ONCE BIT(7) 143 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 144 #define TBG_CNTRL_1_H_TGL BIT(0) 145 #define TBG_CNTRL_1_V_TGL BIT(1) 146 #define TBG_CNTRL_1_TGL_EN BIT(2) 147 #define TBG_CNTRL_1_X_EXT BIT(3) 148 #define TBG_CNTRL_1_H_EXT BIT(4) 149 #define TBG_CNTRL_1_V_EXT BIT(5) 150 #define TBG_CNTRL_1_DWIN_DIS BIT(6) 151 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 152 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 153 #define HVF_CNTRL_0_SM BIT(7) 154 #define HVF_CNTRL_0_RWB BIT(6) 155 #define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 156 #define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 157 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 158 #define HVF_CNTRL_1_FOR BIT(0) 159 #define HVF_CNTRL_1_YUVBLK BIT(1) 160 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 161 #define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 162 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 163 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 164 #define AIP_CLKSEL_AIP_SPDIF (0 << 3) 165 #define AIP_CLKSEL_AIP_I2S BIT(3) 166 #define AIP_CLKSEL_FS_ACLK (0 << 0) 167 #define AIP_CLKSEL_FS_MCLK BIT(0) 168 169 /* Page 02h: PLL settings */ 170 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 171 #define PLL_SERIAL_1_SRL_FDN BIT(0) 172 #define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 173 #define PLL_SERIAL_1_SRL_MAN_IZ BIT(6) 174 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 175 #define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 176 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 177 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 178 #define PLL_SERIAL_3_SRL_CCIR BIT(0) 179 #define PLL_SERIAL_3_SRL_DE BIT(2) 180 #define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4) 181 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 182 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 183 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 184 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 185 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 186 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 187 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 188 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 189 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 190 #define AUDIO_DIV_SERCLK_1 0 191 #define AUDIO_DIV_SERCLK_2 1 192 #define AUDIO_DIV_SERCLK_4 2 193 #define AUDIO_DIV_SERCLK_8 3 194 #define AUDIO_DIV_SERCLK_16 4 195 #define AUDIO_DIV_SERCLK_32 5 196 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 197 #define SEL_CLK_SEL_CLK1 BIT(0) 198 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 199 #define SEL_CLK_ENA_SC_CLK BIT(3) 200 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 201 202 /* Page 09h: EDID Control */ 203 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 204 /* next 127 successive registers are the EDID block */ 205 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 206 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 207 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 208 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 209 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 210 211 /* Page 11h: audio settings and content info packets */ 212 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 213 #define AIP_CNTRL_0_RST_FIFO BIT(0) 214 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 215 #define ENC_CNTRL_RST_ENC BIT(0) 216 #define ENC_CNTRL_RST_SEL BIT(1) 217 #define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 218 219 /* Page 12h: HDCP and OTP */ 220 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 221 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 222 #define TX4_PD_RAM BIT(1) 223 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 224 #define TX33_HDMI BIT(1) 225 226 /* CEC registers, not paged */ 227 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 228 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7) 229 #define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6) 230 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1) 231 #define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0) 232 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 233 #define REG_CEC_RXSHPDINT 0xfd /* read */ 234 #define CEC_RXSHPDINT_RXSENS BIT(0) 235 #define CEC_RXSHPDINT_HPD BIT(1) 236 #define TDA19988_CEC_ENAMODS 0xff /* read/write */ 237 #define CEC_ENAMODS_EN_RXSENS BIT(2) 238 #define CEC_ENAMODS_EN_HDMI BIT(1) 239 #define CEC_ENAMODS_EN_CEC BIT(0) 240 241 /* Device versions */ 242 #define TDA9989N2 0x0101 243 #define TDA19989 0x0201 244 #define TDA19989N2 0x0202 245 #define TDA19988 0x0301 246 247 struct tda19988_priv { 248 struct udevice *chip; 249 struct udevice *cec_chip; 250 u16 revision; 251 u8 current_page; 252 }; 253 254 static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val) 255 { 256 u8 old_val, page = REG2PAGE(reg); 257 258 if (priv->current_page != page) { 259 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); 260 priv->current_page = page; 261 } 262 old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg)); 263 old_val |= val; 264 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val); 265 } 266 267 static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val) 268 { 269 u8 old_val, page = REG2PAGE(reg); 270 271 if (priv->current_page != page) { 272 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); 273 priv->current_page = page; 274 } 275 old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg)); 276 old_val &= ~val; 277 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val); 278 } 279 280 static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val) 281 { 282 u8 page = REG2PAGE(reg); 283 284 if (priv->current_page != page) { 285 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); 286 priv->current_page = page; 287 } 288 dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val); 289 } 290 291 static int tda19988_register_read(struct tda19988_priv *priv, u16 reg) 292 { 293 u8 page = REG2PAGE(reg); 294 295 if (priv->current_page != page) { 296 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); 297 priv->current_page = page; 298 } 299 return dm_i2c_reg_read(priv->chip, REG2ADDR(reg)); 300 } 301 302 static void tda19988_register_write16(struct tda19988_priv *priv, 303 u16 reg, u16 val) 304 { 305 u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg); 306 307 if (priv->current_page != page) { 308 dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); 309 priv->current_page = page; 310 } 311 dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2); 312 } 313 314 static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size) 315 { 316 struct tda19988_priv *priv = dev_get_priv(dev); 317 int i, val = 0, offset = 0; 318 319 /* 320 * The TDA998x has a problem when trying to read the EDID close to a 321 * HPD assertion: it needs a delay of 100ms to avoid timing out while 322 * trying to read EDID data. 323 */ 324 mdelay(120); 325 326 if (priv->revision == TDA19988) 327 tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM); 328 329 while (offset < buf_size) { 330 tda19988_register_write(priv, REG_DDC_ADDR, 0xa0); 331 tda19988_register_write(priv, REG_DDC_OFFS, offset); 332 tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60); 333 tda19988_register_write(priv, REG_DDC_SEGM, 0); 334 335 /* enable reading EDID */ 336 tda19988_register_write(priv, REG_EDID_CTRL, 1); 337 338 /* flags must be cleared by software */ 339 tda19988_register_write(priv, REG_EDID_CTRL, 0); 340 341 /* wait for block read to complete */ 342 for (i = 300; i > 0; i--) { 343 mdelay(1); 344 val = tda19988_register_read(priv, REG_INT_FLAGS_2); 345 if (val < 0) 346 return val; 347 if (val & INT_FLAGS_2_EDID_BLK_RD) 348 break; 349 } 350 351 if (i == 0) 352 return -ETIMEDOUT; 353 354 priv->current_page = REG2PAGE(REG_EDID_DATA_0); 355 dm_i2c_reg_write(priv->chip, 356 REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0)); 357 val = dm_i2c_read(priv->chip, 358 REG2ADDR(REG_EDID_DATA_0), buf + offset, 128); 359 offset += 128; 360 } 361 362 if (priv->revision == TDA19988) 363 tda19988_register_set(priv, REG_TX4, TX4_PD_RAM); 364 365 return offset; 366 } 367 368 static int tda19988_enable(struct udevice *dev, int panel_bpp, 369 const struct display_timing *timing) 370 { 371 struct tda19988_priv *priv = dev_get_priv(dev); 372 u8 div = 148500000 / timing->pixelclock.typ, reg; 373 u16 line_clocks, lines; 374 375 if (dev != 0) { 376 div--; 377 if (div > 3) 378 div = 3; 379 } 380 /* first disable the video ports */ 381 tda19988_register_write(priv, REG_ENA_VP_0, 0); 382 tda19988_register_write(priv, REG_ENA_VP_1, 0); 383 tda19988_register_write(priv, REG_ENA_VP_2, 0); 384 385 /* shutdown audio */ 386 tda19988_register_write(priv, REG_ENA_AP, 0); 387 388 line_clocks = timing->hsync_len.typ + timing->hback_porch.typ + 389 timing->hactive.typ + timing->hfront_porch.typ; 390 lines = timing->vsync_len.typ + timing->vback_porch.typ + 391 timing->vactive.typ + timing->vfront_porch.typ; 392 393 /* mute the audio FIFO */ 394 tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 395 /* HDMI HDCP: off */ 396 tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 397 tda19988_register_clear(priv, REG_TX33, TX33_HDMI); 398 tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 399 400 /* no pre-filter or interpolator */ 401 tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 402 HVF_CNTRL_0_INTPOL(0)); 403 tda19988_register_set(priv, REG_FEAT_POWERDOWN, 404 FEAT_POWERDOWN_PREFILT); 405 tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 406 tda19988_register_write(priv, REG_VIP_CNTRL_4, 407 VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) | 408 VIP_CNTRL_4_TST_PAT); 409 410 tda19988_register_clear(priv, REG_PLL_SERIAL_1, 411 PLL_SERIAL_1_SRL_MAN_IZ); 412 tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | 413 PLL_SERIAL_3_SRL_DE); 414 415 tda19988_register_write(priv, REG_SERIALIZER, 0); 416 tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 417 418 tda19988_register_write(priv, REG_RPT_CNTRL, 0); 419 tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 420 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 421 tda19988_register_write(priv, REG_PLL_SERIAL_2, 422 PLL_SERIAL_2_SRL_NOSC(div) | 423 PLL_SERIAL_2_SRL_PR(0)); 424 425 /* set color matrix bypass flag: */ 426 tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 427 MAT_CONTRL_MAT_SC(1)); 428 tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 429 430 /* set BIAS tmds value: */ 431 tda19988_register_write(priv, REG_ANA_GENERAL, 0x09); 432 433 /* 434 * Sync on rising HSYNC/VSYNC 435 */ 436 reg = VIP_CNTRL_3_SYNC_HS; 437 438 /* 439 * TDA19988 requires high-active sync at input stage, 440 * so invert low-active sync provided by master encoder here 441 */ 442 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) 443 reg |= VIP_CNTRL_3_H_TGL; 444 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) 445 reg |= VIP_CNTRL_3_V_TGL; 446 tda19988_register_write(priv, REG_VIP_CNTRL_3, reg); 447 448 tda19988_register_write(priv, REG_VIDFORMAT, 0x00); 449 tda19988_register_write16(priv, REG_REFPIX_MSB, 450 timing->hfront_porch.typ + 3); 451 tda19988_register_write16(priv, REG_REFLINE_MSB, 452 timing->vfront_porch.typ + 1); 453 tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks); 454 tda19988_register_write16(priv, REG_NLINE_MSB, lines); 455 tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB, 456 timing->vfront_porch.typ); 457 tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB, 458 timing->hfront_porch.typ); 459 tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB, 460 timing->vfront_porch.typ + 461 timing->vsync_len.typ); 462 tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB, 463 timing->hfront_porch.typ); 464 tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0); 465 tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0); 466 tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0); 467 tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0); 468 tda19988_register_write16(priv, REG_HS_PIX_START_MSB, 469 timing->hfront_porch.typ); 470 tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB, 471 timing->hfront_porch.typ + 472 timing->hsync_len.typ); 473 tda19988_register_write16(priv, REG_VWIN_START_1_MSB, 474 lines - timing->vactive.typ - 1); 475 tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1); 476 tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0); 477 tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0); 478 tda19988_register_write16(priv, REG_DE_START_MSB, 479 line_clocks - timing->hactive.typ); 480 tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks); 481 482 if (priv->revision == TDA19988) { 483 /* let incoming pixels fill the active space (if any) */ 484 tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00); 485 } 486 487 /* 488 * Always generate sync polarity relative to input sync and 489 * revert input stage toggled sync at output stage 490 */ 491 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 492 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) 493 reg |= TBG_CNTRL_1_H_TGL; 494 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) 495 reg |= TBG_CNTRL_1_V_TGL; 496 tda19988_register_write(priv, REG_TBG_CNTRL_1, reg); 497 498 /* must be last register set: */ 499 tda19988_register_write(priv, REG_TBG_CNTRL_0, 0); 500 501 /* turn on HDMI HDCP */ 502 reg &= ~TBG_CNTRL_1_DWIN_DIS; 503 tda19988_register_write(priv, REG_TBG_CNTRL_1, reg); 504 tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 505 tda19988_register_set(priv, REG_TX33, TX33_HDMI); 506 507 mdelay(400); 508 509 /* enable video ports */ 510 tda19988_register_write(priv, REG_ENA_VP_0, 0xff); 511 tda19988_register_write(priv, REG_ENA_VP_1, 0xff); 512 tda19988_register_write(priv, REG_ENA_VP_2, 0xff); 513 /* set muxing after enabling ports: */ 514 tda19988_register_write(priv, REG_VIP_CNTRL_0, 515 VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3)); 516 tda19988_register_write(priv, REG_VIP_CNTRL_1, 517 VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5)); 518 tda19988_register_write(priv, REG_VIP_CNTRL_2, 519 VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1)); 520 521 return 0; 522 } 523 524 struct dm_display_ops tda19988_ops = { 525 .read_edid = tda19988_read_edid, 526 .enable = tda19988_enable, 527 }; 528 529 static const struct udevice_id tda19988_ids[] = { 530 { .compatible = "nxp,tda998x" }, 531 { } 532 }; 533 534 static int tda19988_probe(struct udevice *dev) 535 { 536 u8 cec_addr, chip_addr, rev_lo, rev_hi; 537 int err; 538 struct tda19988_priv *priv = dev_get_priv(dev); 539 540 chip_addr = dev_read_addr(dev); 541 /* CEC I2C address is using TDA19988 I2C address configuration pins */ 542 cec_addr = 0x34 + (chip_addr & 0x03); 543 544 err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip); 545 if (err) { 546 printf("cec i2c_get_chip_for_busnum returned %d\n", err); 547 return err; 548 } 549 550 err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip); 551 if (err) { 552 printf("i2c_get_chip_for_busnum returned %d\n", err); 553 return err; 554 } 555 556 priv->current_page = 0xff; 557 558 /* wake up device */ 559 dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS, 560 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 561 562 /* reset audio and I2C master */ 563 tda19988_register_write(priv, REG_SOFTRESET, 564 SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 565 mdelay(50); 566 tda19988_register_write(priv, REG_SOFTRESET, 0); 567 mdelay(50); 568 569 /* reset transmitter */ 570 tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 571 tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 572 573 /* PLL registers common configuration */ 574 tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00); 575 tda19988_register_write(priv, REG_PLL_SERIAL_2, 576 PLL_SERIAL_2_SRL_NOSC(1)); 577 tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00); 578 tda19988_register_write(priv, REG_SERIALIZER, 0x00); 579 tda19988_register_write(priv, REG_BUFFER_OUT, 0x00); 580 tda19988_register_write(priv, REG_PLL_SCG1, 0x00); 581 tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 582 tda19988_register_write(priv, REG_SEL_CLK, 583 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 584 tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa); 585 tda19988_register_write(priv, REG_PLL_SCGN2, 0x00); 586 tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b); 587 tda19988_register_write(priv, REG_PLL_SCGR2, 0x00); 588 tda19988_register_write(priv, REG_PLL_SCG2, 0x10); 589 590 /* Write the default value MUX register */ 591 tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 592 593 /* read version */ 594 rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB); 595 rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB); 596 597 /* mask off feature bits */ 598 priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30; 599 600 printf("HDMI: "); 601 switch (priv->revision) { 602 case TDA9989N2: 603 printf("TDA9989 n2\n"); 604 break; 605 case TDA19989: 606 printf("TDA19989\n"); 607 break; 608 case TDA19989N2: 609 printf("TDA19989 n2\n"); 610 break; 611 case TDA19988: 612 printf("TDA19988\n"); 613 break; 614 default: 615 printf("unknown TDA device: 0x%04x\n", priv->revision); 616 return -ENXIO; 617 } 618 619 /* after reset, enable DDC */ 620 tda19988_register_write(priv, REG_DDC_DISABLE, 0x00); 621 622 /* set clock on DDC channel */ 623 tda19988_register_write(priv, REG_TX3, 39); 624 625 /* if necessary, disable multi-master */ 626 if (priv->revision == TDA19989) 627 tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 628 629 dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL, 630 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | 631 CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 632 /* ensure interrupts are disabled */ 633 dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0); 634 /* clear pending interrupts */ 635 dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT); 636 tda19988_register_read(priv, REG_INT_FLAGS_0); 637 tda19988_register_read(priv, REG_INT_FLAGS_1); 638 tda19988_register_read(priv, REG_INT_FLAGS_2); 639 640 /* enable EDID read irq */ 641 tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 642 643 return 0; 644 } 645 646 U_BOOT_DRIVER(tda19988) = { 647 .name = "tda19988", 648 .id = UCLASS_DISPLAY, 649 .of_match = tda19988_ids, 650 .ops = &tda19988_ops, 651 .probe = tda19988_probe, 652 .priv_auto_alloc_size = sizeof(struct tda19988_priv), 653 }; 654