1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Allwinner DW HDMI bridge
4  *
5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
6  */
7 
8 #include <common.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <dw_hdmi.h>
12 #include <edid.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/lcdc.h>
16 
17 struct sunxi_dw_hdmi_priv {
18 	struct dw_hdmi hdmi;
19 	int mux;
20 };
21 
22 struct sunxi_hdmi_phy {
23 	u32 pol;
24 	u32 res1[3];
25 	u32 read_en;
26 	u32 unscramble;
27 	u32 res2[2];
28 	u32 ctrl;
29 	u32 unk1;
30 	u32 unk2;
31 	u32 pll;
32 	u32 clk;
33 	u32 unk3;
34 	u32 status;
35 };
36 
37 #define HDMI_PHY_OFFS 0x10000
38 
39 static int sunxi_dw_hdmi_get_divider(uint clock)
40 {
41 	/*
42 	 * Due to missing documentaion of HDMI PHY, we know correct
43 	 * settings only for following four PHY dividers. Select one
44 	 * based on clock speed.
45 	 */
46 	if (clock <= 27000000)
47 		return 11;
48 	else if (clock <= 74250000)
49 		return 4;
50 	else if (clock <= 148500000)
51 		return 2;
52 	else
53 		return 1;
54 }
55 
56 static void sunxi_dw_hdmi_phy_init(void)
57 {
58 	struct sunxi_hdmi_phy * const phy =
59 		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
60 	unsigned long tmo;
61 	u32 tmp;
62 
63 	/*
64 	 * HDMI PHY settings are taken as-is from Allwinner BSP code.
65 	 * There is no documentation.
66 	 */
67 	writel(0, &phy->ctrl);
68 	setbits_le32(&phy->ctrl, BIT(0));
69 	udelay(5);
70 	setbits_le32(&phy->ctrl, BIT(16));
71 	setbits_le32(&phy->ctrl, BIT(1));
72 	udelay(10);
73 	setbits_le32(&phy->ctrl, BIT(2));
74 	udelay(5);
75 	setbits_le32(&phy->ctrl, BIT(3));
76 	udelay(40);
77 	setbits_le32(&phy->ctrl, BIT(19));
78 	udelay(100);
79 	setbits_le32(&phy->ctrl, BIT(18));
80 	setbits_le32(&phy->ctrl, 7 << 4);
81 
82 	/* Note that Allwinner code doesn't fail in case of timeout */
83 	tmo = timer_get_us() + 2000;
84 	while ((readl(&phy->status) & 0x80) == 0) {
85 		if (timer_get_us() > tmo) {
86 			printf("Warning: HDMI PHY init timeout!\n");
87 			break;
88 		}
89 	}
90 
91 	setbits_le32(&phy->ctrl, 0xf << 8);
92 	setbits_le32(&phy->ctrl, BIT(7));
93 
94 	writel(0x39dc5040, &phy->pll);
95 	writel(0x80084343, &phy->clk);
96 	udelay(10000);
97 	writel(1, &phy->unk3);
98 	setbits_le32(&phy->pll, BIT(25));
99 	udelay(100000);
100 	tmp = (readl(&phy->status) & 0x1f800) >> 11;
101 	setbits_le32(&phy->pll, BIT(31) | BIT(30));
102 	setbits_le32(&phy->pll, tmp);
103 	writel(0x01FF0F7F, &phy->ctrl);
104 	writel(0x80639000, &phy->unk1);
105 	writel(0x0F81C405, &phy->unk2);
106 
107 	/* enable read access to HDMI controller */
108 	writel(0x54524545, &phy->read_en);
109 	/* descramble register offsets */
110 	writel(0x42494E47, &phy->unscramble);
111 }
112 
113 static int sunxi_dw_hdmi_get_plug_in_status(void)
114 {
115 	struct sunxi_hdmi_phy * const phy =
116 		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
117 
118 	return !!(readl(&phy->status) & (1 << 19));
119 }
120 
121 static int sunxi_dw_hdmi_wait_for_hpd(void)
122 {
123 	ulong start;
124 
125 	start = get_timer(0);
126 	do {
127 		if (sunxi_dw_hdmi_get_plug_in_status())
128 			return 0;
129 		udelay(100);
130 	} while (get_timer(start) < 300);
131 
132 	return -1;
133 }
134 
135 static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
136 {
137 	struct sunxi_hdmi_phy * const phy =
138 		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
139 	int div = sunxi_dw_hdmi_get_divider(clock);
140 	u32 tmp;
141 
142 	/*
143 	 * Unfortunately, we don't know much about those magic
144 	 * numbers. They are taken from Allwinner BSP driver.
145 	 */
146 	switch (div) {
147 	case 1:
148 		writel(0x30dc5fc0, &phy->pll);
149 		writel(0x800863C0 | (phy_div - 1), &phy->clk);
150 		mdelay(10);
151 		writel(0x00000001, &phy->unk3);
152 		setbits_le32(&phy->pll, BIT(25));
153 		mdelay(200);
154 		tmp = (readl(&phy->status) & 0x1f800) >> 11;
155 		setbits_le32(&phy->pll, BIT(31) | BIT(30));
156 		if (tmp < 0x3d)
157 			setbits_le32(&phy->pll, tmp + 2);
158 		else
159 			setbits_le32(&phy->pll, 0x3f);
160 		mdelay(100);
161 		writel(0x01FFFF7F, &phy->ctrl);
162 		writel(0x8063b000, &phy->unk1);
163 		writel(0x0F8246B5, &phy->unk2);
164 		break;
165 	case 2:
166 		writel(0x39dc5040, &phy->pll);
167 		writel(0x80084380 | (phy_div - 1), &phy->clk);
168 		mdelay(10);
169 		writel(0x00000001, &phy->unk3);
170 		setbits_le32(&phy->pll, BIT(25));
171 		mdelay(100);
172 		tmp = (readl(&phy->status) & 0x1f800) >> 11;
173 		setbits_le32(&phy->pll, BIT(31) | BIT(30));
174 		setbits_le32(&phy->pll, tmp);
175 		writel(0x01FFFF7F, &phy->ctrl);
176 		writel(0x8063a800, &phy->unk1);
177 		writel(0x0F81C485, &phy->unk2);
178 		break;
179 	case 4:
180 		writel(0x39dc5040, &phy->pll);
181 		writel(0x80084340 | (phy_div - 1), &phy->clk);
182 		mdelay(10);
183 		writel(0x00000001, &phy->unk3);
184 		setbits_le32(&phy->pll, BIT(25));
185 		mdelay(100);
186 		tmp = (readl(&phy->status) & 0x1f800) >> 11;
187 		setbits_le32(&phy->pll, BIT(31) | BIT(30));
188 		setbits_le32(&phy->pll, tmp);
189 		writel(0x01FFFF7F, &phy->ctrl);
190 		writel(0x8063b000, &phy->unk1);
191 		writel(0x0F81C405, &phy->unk2);
192 		break;
193 	case 11:
194 		writel(0x39dc5040, &phy->pll);
195 		writel(0x80084300 | (phy_div - 1), &phy->clk);
196 		mdelay(10);
197 		writel(0x00000001, &phy->unk3);
198 		setbits_le32(&phy->pll, BIT(25));
199 		mdelay(100);
200 		tmp = (readl(&phy->status) & 0x1f800) >> 11;
201 		setbits_le32(&phy->pll, BIT(31) | BIT(30));
202 		setbits_le32(&phy->pll, tmp);
203 		writel(0x01FFFF7F, &phy->ctrl);
204 		writel(0x8063b000, &phy->unk1);
205 		writel(0x0F81C405, &phy->unk2);
206 		break;
207 	}
208 }
209 
210 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
211 {
212 	int value, n, m, div, diff;
213 	int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
214 
215 	/*
216 	 * Find the lowest divider resulting in a matching clock. If there
217 	 * is no match, pick the closest lower clock, as monitors tend to
218 	 * not sync to higher frequencies.
219 	 */
220 	for (div = 1; div <= 16; div++) {
221 		int target = clk_khz * div;
222 
223 		if (target < 192000)
224 			continue;
225 		if (target > 912000)
226 			continue;
227 
228 		for (m = 1; m <= 16; m++) {
229 			n = (m * target) / 24000;
230 
231 			if (n >= 1 && n <= 128) {
232 				value = (24000 * n) / m / div;
233 				diff = clk_khz - value;
234 				if (diff < best_diff) {
235 					best_diff = diff;
236 					best_m = m;
237 					best_n = n;
238 					best_div = div;
239 				}
240 			}
241 		}
242 	}
243 
244 	*phy_div = best_div;
245 
246 	clock_set_pll3_factors(best_m, best_n);
247 	debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
248 	      clk_khz, (clock_get_pll3() / 1000) / best_div,
249 	      best_n, best_m, best_div);
250 }
251 
252 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
253 				    int bpp)
254 {
255 	struct sunxi_ccm_reg * const ccm =
256 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
257 	int div = clock_get_pll3() / edid->pixelclock.typ;
258 	struct sunxi_lcdc_reg *lcdc;
259 
260 	if (mux == 0) {
261 		lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
262 
263 		/* Reset off */
264 		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
265 
266 		/* Clock on */
267 		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
268 		writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
269 		       &ccm->lcd0_clk_cfg);
270 	} else {
271 		lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
272 
273 		/* Reset off */
274 		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
275 
276 		/* Clock on */
277 		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
278 		writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
279 		       &ccm->lcd1_clk_cfg);
280 	}
281 
282 	lcdc_init(lcdc);
283 	lcdc_tcon1_mode_set(lcdc, edid, false, false);
284 	lcdc_enable(lcdc, bpp);
285 }
286 
287 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
288 {
289 	int phy_div;
290 
291 	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
292 	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
293 
294 	return 0;
295 }
296 
297 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
298 {
299 	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
300 
301 	return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
302 }
303 
304 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
305 				const struct display_timing *edid)
306 {
307 	struct sunxi_hdmi_phy * const phy =
308 		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
309 	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
310 	int ret;
311 
312 	ret = dw_hdmi_enable(&priv->hdmi, edid);
313 	if (ret)
314 		return ret;
315 
316 	sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
317 
318 	if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
319 		setbits_le32(&phy->pol, 0x200);
320 
321 	if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
322 		setbits_le32(&phy->pol, 0x100);
323 
324 	setbits_le32(&phy->ctrl, 0xf << 12);
325 
326 	/*
327 	 * This is last hdmi access before boot, so scramble addresses
328 	 * again or othwerwise BSP driver won't work. Dummy read is
329 	 * needed or otherwise last write doesn't get written correctly.
330 	 */
331 	(void)readb(SUNXI_HDMI_BASE);
332 	writel(0, &phy->unscramble);
333 
334 	return 0;
335 }
336 
337 static int sunxi_dw_hdmi_probe(struct udevice *dev)
338 {
339 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
340 	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
341 	struct sunxi_ccm_reg * const ccm =
342 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
343 	int ret;
344 
345 	/* Set pll3 to 297 MHz */
346 	clock_set_pll3(297000000);
347 
348 	/* Set hdmi parent to pll3 */
349 	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
350 			CCM_HDMI_CTRL_PLL3);
351 
352 	/* Set ahb gating to pass */
353 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
354 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
355 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
356 	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
357 
358 	/* Clock on */
359 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
360 
361 	sunxi_dw_hdmi_phy_init();
362 
363 	ret = sunxi_dw_hdmi_wait_for_hpd();
364 	if (ret < 0) {
365 		debug("hdmi can not get hpd signal\n");
366 		return -1;
367 	}
368 
369 	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
370 	priv->hdmi.i2c_clk_high = 0xd8;
371 	priv->hdmi.i2c_clk_low = 0xfe;
372 	priv->hdmi.reg_io_width = 1;
373 	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
374 	priv->mux = uc_plat->source_id;
375 
376 	dw_hdmi_init(&priv->hdmi);
377 
378 	return 0;
379 }
380 
381 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
382 	.read_edid = sunxi_dw_hdmi_read_edid,
383 	.enable = sunxi_dw_hdmi_enable,
384 };
385 
386 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
387 	.name	= "sunxi_dw_hdmi",
388 	.id	= UCLASS_DISPLAY,
389 	.ops	= &sunxi_dw_hdmi_ops,
390 	.probe	= sunxi_dw_hdmi_probe,
391 	.priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
392 };
393 
394 U_BOOT_DEVICE(sunxi_dw_hdmi) = {
395 	.name = "sunxi_dw_hdmi"
396 };
397