1 /* 2 * Allwinner DE2 display driver 3 * 4 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <edid.h> 13 #include <video.h> 14 #include <asm/global_data.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/display2.h> 18 #include <dm/device-internal.h> 19 #include <dm/uclass-internal.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 enum { 24 /* Maximum LCD size we support */ 25 LCD_MAX_WIDTH = 3840, 26 LCD_MAX_HEIGHT = 2160, 27 LCD_MAX_LOG2_BPP = VIDEO_BPP32, 28 }; 29 30 static void sunxi_de2_composer_init(void) 31 { 32 struct sunxi_ccm_reg * const ccm = 33 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 34 35 #ifdef CONFIG_MACH_SUN50I 36 u32 reg_value; 37 38 /* set SRAM for video use (A64 only) */ 39 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); 40 reg_value &= ~(0x01 << 24); 41 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); 42 #endif 43 44 clock_set_pll10(432000000); 45 46 /* Set DE parent to pll10 */ 47 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, 48 CCM_DE2_CTRL_PLL10); 49 50 /* Set ahb gating to pass */ 51 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); 52 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); 53 54 /* Clock on */ 55 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); 56 } 57 58 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, 59 int bpp, ulong address) 60 { 61 ulong de_mux_base = (mux == 0) ? 62 SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE; 63 struct de_clk * const de_clk_regs = 64 (struct de_clk *)(SUNXI_DE2_BASE); 65 struct de_glb * const de_glb_regs = 66 (struct de_glb *)(de_mux_base + 67 SUNXI_DE2_MUX_GLB_REGS); 68 struct de_bld * const de_bld_regs = 69 (struct de_bld *)(de_mux_base + 70 SUNXI_DE2_MUX_BLD_REGS); 71 struct de_ui * const de_ui_regs = 72 (struct de_ui *)(de_mux_base + 73 SUNXI_DE2_MUX_CHAN_REGS + 74 SUNXI_DE2_MUX_CHAN_SZ * 1); 75 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); 76 int channel; 77 u32 format; 78 79 /* enable clock */ 80 #ifdef CONFIG_MACH_SUN8I_H3 81 setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); 82 #else 83 setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); 84 #endif 85 setbits_le32(&de_clk_regs->gate_cfg, BIT(mux)); 86 setbits_le32(&de_clk_regs->bus_cfg, BIT(mux)); 87 88 clrbits_le32(&de_clk_regs->sel_cfg, 1); 89 90 writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl); 91 writel(0, &de_glb_regs->status); 92 writel(1, &de_glb_regs->dbuff); 93 writel(size, &de_glb_regs->size); 94 95 for (channel = 0; channel < 4; channel++) { 96 void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS + 97 SUNXI_DE2_MUX_CHAN_SZ * channel); 98 memset(ch, 0, (channel == 0) ? 99 sizeof(struct de_vi) : sizeof(struct de_ui)); 100 } 101 memset(de_bld_regs, 0, sizeof(struct de_bld)); 102 103 writel(0x00000101, &de_bld_regs->fcolor_ctl); 104 105 writel(1, &de_bld_regs->route); 106 107 writel(0, &de_bld_regs->premultiply); 108 writel(0xff000000, &de_bld_regs->bkcolor); 109 110 writel(0x03010301, &de_bld_regs->bld_mode[0]); 111 112 writel(size, &de_bld_regs->output_size); 113 writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0, 114 &de_bld_regs->out_ctl); 115 writel(0, &de_bld_regs->ck_ctl); 116 117 writel(0xff000000, &de_bld_regs->attr[0].fcolor); 118 writel(size, &de_bld_regs->attr[0].insize); 119 120 /* Disable all other units */ 121 writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS); 122 writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS); 123 writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS); 124 writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS); 125 writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS); 126 writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS); 127 writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS); 128 writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS); 129 writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS); 130 writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS); 131 writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS); 132 133 switch (bpp) { 134 case 16: 135 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565); 136 break; 137 case 32: 138 default: 139 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888); 140 break; 141 } 142 143 writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr); 144 writel(size, &de_ui_regs->cfg[0].size); 145 writel(0, &de_ui_regs->cfg[0].coord); 146 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch); 147 writel(address, &de_ui_regs->cfg[0].top_laddr); 148 writel(size, &de_ui_regs->ovl_size); 149 150 /* apply settings */ 151 writel(1, &de_glb_regs->dbuff); 152 } 153 154 static int sunxi_de2_init(struct udevice *dev, ulong fbbase, 155 enum video_log2_bpp l2bpp, 156 struct udevice *disp, int mux) 157 { 158 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 159 struct display_timing timing; 160 struct display_plat *disp_uc_plat; 161 int ret; 162 163 disp_uc_plat = dev_get_uclass_platdata(disp); 164 debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); 165 if (display_in_use(disp)) { 166 debug(" - device in use\n"); 167 return -EBUSY; 168 } 169 170 disp_uc_plat->source_id = mux; 171 172 ret = device_probe(disp); 173 if (ret) { 174 debug("%s: device '%s' display won't probe (ret=%d)\n", 175 __func__, dev->name, ret); 176 return ret; 177 } 178 179 ret = display_read_timing(disp, &timing); 180 if (ret) { 181 debug("%s: Failed to read timings\n", __func__); 182 return ret; 183 } 184 185 sunxi_de2_composer_init(); 186 sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase); 187 188 ret = display_enable(disp, 1 << l2bpp, &timing); 189 if (ret) { 190 debug("%s: Failed to enable display\n", __func__); 191 return ret; 192 } 193 194 uc_priv->xsize = timing.hactive.typ; 195 uc_priv->ysize = timing.vactive.typ; 196 uc_priv->bpix = l2bpp; 197 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize); 198 199 return 0; 200 } 201 202 static int sunxi_de2_probe(struct udevice *dev) 203 { 204 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 205 struct udevice *disp; 206 int ret; 207 int mux; 208 209 /* Before relocation we don't need to do anything */ 210 if (!(gd->flags & GD_FLG_RELOC)) 211 return 0; 212 213 ret = uclass_find_device_by_name(UCLASS_DISPLAY, 214 "sunxi_dw_hdmi", &disp); 215 if (ret) { 216 debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); 217 return ret; 218 } 219 220 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) 221 mux = 0; 222 else 223 mux = 1; 224 225 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux); 226 if (ret) 227 return ret; 228 229 video_set_flush_dcache(dev, 1); 230 231 return 0; 232 } 233 234 static int sunxi_de2_bind(struct udevice *dev) 235 { 236 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 237 238 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * 239 (1 << LCD_MAX_LOG2_BPP) / 8; 240 241 return 0; 242 } 243 244 static const struct video_ops sunxi_de2_ops = { 245 }; 246 247 U_BOOT_DRIVER(sunxi_de2) = { 248 .name = "sunxi_de2", 249 .id = UCLASS_VIDEO, 250 .ops = &sunxi_de2_ops, 251 .bind = sunxi_de2_bind, 252 .probe = sunxi_de2_probe, 253 .flags = DM_FLAG_PRE_RELOC, 254 }; 255 256 U_BOOT_DEVICE(sunxi_de2) = { 257 .name = "sunxi_de2" 258 }; 259