1 /* 2 * Copyright (C) STMicroelectronics SA 2017 3 * 4 * Authors: Philippe Cornu <philippe.cornu@st.com> 5 * Yannick Fertre <yannick.fertre@st.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <panel.h> 14 #include <reset.h> 15 #include <video.h> 16 #include <asm/io.h> 17 #include <asm/arch/gpio.h> 18 #include <dm/device-internal.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 struct stm32_ltdc_priv { 23 void __iomem *regs; 24 struct display_timing timing; 25 enum video_log2_bpp l2bpp; 26 u32 bg_col_argb; 27 u32 crop_x, crop_y, crop_w, crop_h; 28 u32 alpha; 29 }; 30 31 /* LTDC main registers */ 32 #define LTDC_IDR 0x00 /* IDentification */ 33 #define LTDC_LCR 0x04 /* Layer Count */ 34 #define LTDC_SSCR 0x08 /* Synchronization Size Configuration */ 35 #define LTDC_BPCR 0x0C /* Back Porch Configuration */ 36 #define LTDC_AWCR 0x10 /* Active Width Configuration */ 37 #define LTDC_TWCR 0x14 /* Total Width Configuration */ 38 #define LTDC_GCR 0x18 /* Global Control */ 39 #define LTDC_GC1R 0x1C /* Global Configuration 1 */ 40 #define LTDC_GC2R 0x20 /* Global Configuration 2 */ 41 #define LTDC_SRCR 0x24 /* Shadow Reload Configuration */ 42 #define LTDC_GACR 0x28 /* GAmma Correction */ 43 #define LTDC_BCCR 0x2C /* Background Color Configuration */ 44 #define LTDC_IER 0x34 /* Interrupt Enable */ 45 #define LTDC_ISR 0x38 /* Interrupt Status */ 46 #define LTDC_ICR 0x3C /* Interrupt Clear */ 47 #define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */ 48 #define LTDC_CPSR 0x44 /* Current Position Status */ 49 #define LTDC_CDSR 0x48 /* Current Display Status */ 50 51 /* LTDC layer 1 registers */ 52 #define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */ 53 #define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */ 54 #define LTDC_L1CR 0x84 /* L1 Control */ 55 #define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */ 56 #define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */ 57 #define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */ 58 #define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */ 59 #define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */ 60 #define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */ 61 #define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */ 62 #define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */ 63 #define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */ 64 #define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */ 65 #define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */ 66 #define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */ 67 #define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */ 68 #define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */ 69 #define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */ 70 #define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */ 71 72 /* Bit definitions */ 73 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 74 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 75 76 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 77 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 78 79 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 80 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 81 82 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 83 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 84 85 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 86 #define GCR_DEN BIT(16) /* Dither ENable */ 87 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 88 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 89 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 90 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 91 92 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 93 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 94 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 95 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 96 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 97 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 98 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 99 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 100 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 101 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 102 #define GC1R_TP BIT(25) /* Timing Programmable */ 103 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 104 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 105 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 106 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 107 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 108 109 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 110 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 111 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 112 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 113 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 114 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 115 116 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 117 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 118 119 #define LXCR_LEN BIT(0) /* Layer ENable */ 120 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 121 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 122 123 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 124 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 125 126 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 127 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 128 129 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 130 131 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 132 133 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 134 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 135 136 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 137 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 138 139 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 140 141 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 142 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 143 144 enum stm32_ltdc_pix_fmt { 145 PF_ARGB8888 = 0, 146 PF_RGB888, 147 PF_RGB565, 148 PF_ARGB1555, 149 PF_ARGB4444, 150 PF_L8, 151 PF_AL44, 152 PF_AL88 153 }; 154 155 /* TODO add more color format support */ 156 static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp) 157 { 158 enum stm32_ltdc_pix_fmt pf; 159 160 switch (l2bpp) { 161 case VIDEO_BPP16: 162 pf = PF_RGB565; 163 break; 164 165 case VIDEO_BPP1: 166 case VIDEO_BPP2: 167 case VIDEO_BPP4: 168 case VIDEO_BPP8: 169 case VIDEO_BPP32: 170 default: 171 debug("%s: warning %dbpp not supported yet, %dbpp instead\n", 172 __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16)); 173 pf = PF_RGB565; 174 break; 175 } 176 177 debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf); 178 179 return (u32)pf; 180 } 181 182 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv) 183 { 184 /* Reload configuration immediately & enable LTDC */ 185 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR); 186 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN); 187 } 188 189 static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv) 190 { 191 void __iomem *regs = priv->regs; 192 struct display_timing *timing = &priv->timing; 193 u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h; 194 u32 total_w, total_h; 195 u32 val; 196 197 /* Convert video timings to ltdc timings */ 198 hsync = timing->hsync_len.typ - 1; 199 vsync = timing->vsync_len.typ - 1; 200 acc_hbp = hsync + timing->hback_porch.typ; 201 acc_vbp = vsync + timing->vback_porch.typ; 202 acc_act_w = acc_hbp + timing->hactive.typ; 203 acc_act_h = acc_vbp + timing->vactive.typ; 204 total_w = acc_act_w + timing->hfront_porch.typ; 205 total_h = acc_act_h + timing->vfront_porch.typ; 206 207 /* Synchronization sizes */ 208 val = (hsync << 16) | vsync; 209 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 210 211 /* Accumulated back porch */ 212 val = (acc_hbp << 16) | acc_vbp; 213 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 214 215 /* Accumulated active width */ 216 val = (acc_act_w << 16) | acc_act_h; 217 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 218 219 /* Total width & height */ 220 val = (total_w << 16) | total_h; 221 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 222 223 /* Signal polarities */ 224 val = 0; 225 debug("%s: timing->flags 0x%08x\n", __func__, timing->flags); 226 if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH) 227 val |= GCR_HSPOL; 228 if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH) 229 val |= GCR_VSPOL; 230 if (timing->flags & DISPLAY_FLAGS_DE_HIGH) 231 val |= GCR_DEPOL; 232 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 233 val |= GCR_PCPOL; 234 clrsetbits_le32(regs + LTDC_GCR, 235 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 236 237 /* Overall background color */ 238 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR); 239 } 240 241 static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) 242 { 243 void __iomem *regs = priv->regs; 244 u32 x0, x1, y0, y1; 245 u32 pitch_in_bytes; 246 u32 line_length; 247 u32 bus_width; 248 u32 val, tmp, bpp; 249 250 x0 = priv->crop_x; 251 x1 = priv->crop_x + priv->crop_w - 1; 252 y0 = priv->crop_y; 253 y1 = priv->crop_y + priv->crop_h - 1; 254 255 /* Horizontal start and stop position */ 256 tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16; 257 val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp); 258 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, 259 val); 260 261 /* Vertical start & stop position */ 262 tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP; 263 val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp); 264 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, 265 val); 266 267 /* Layer background color */ 268 writel(priv->bg_col_argb, regs + LTDC_L1DCCR); 269 270 /* Color frame buffer pitch in bytes & line length */ 271 bpp = VNBITS(priv->l2bpp); 272 pitch_in_bytes = priv->crop_w * (bpp >> 3); 273 bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4); 274 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1; 275 val = (pitch_in_bytes << 16) | line_length; 276 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 277 278 /* Pixel format */ 279 val = stm32_ltdc_get_pixel_format(priv->l2bpp); 280 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val); 281 282 /* Constant alpha value */ 283 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha); 284 285 /* Blending factors */ 286 clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, 287 BF1_PAXCA | BF2_1PAXCA); 288 289 /* Frame buffer line number */ 290 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h); 291 292 /* Frame buffer address */ 293 writel(fb_addr, regs + LTDC_L1CFBAR); 294 295 /* Enable layer 1 */ 296 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN); 297 } 298 299 static int stm32_ltdc_probe(struct udevice *dev) 300 { 301 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); 302 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 303 struct stm32_ltdc_priv *priv = dev_get_priv(dev); 304 struct udevice *panel; 305 struct clk pclk, pxclk; 306 struct reset_ctl rst; 307 int ret; 308 309 priv->regs = (void *)dev_read_addr(dev); 310 if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { 311 debug("%s: ltdc dt register address error\n", __func__); 312 return -EINVAL; 313 } 314 315 ret = uclass_first_device(UCLASS_PANEL, &panel); 316 if (ret) { 317 debug("%s: panel device error %d\n", __func__, ret); 318 return ret; 319 } 320 321 ret = reset_get_by_index(dev, 0, &rst); 322 if (ret) { 323 debug("%s: missing ltdc hardware reset\n", __func__); 324 return -ENODEV; 325 } 326 327 /* Reset */ 328 reset_deassert(&rst); 329 330 ret = panel_enable_backlight(panel); 331 if (ret) { 332 debug("%s: panel %s enable backlight error %d\n", 333 __func__, panel->name, ret); 334 return ret; 335 } 336 337 ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), 338 0, &priv->timing); 339 if (ret) { 340 debug("%s: decode display timing error %d\n", __func__, ret); 341 return -EINVAL; 342 } 343 344 ret = clk_get_by_name(dev, "pclk", &pclk); 345 if (ret) { 346 debug("%s: peripheral clock get error %d\n", __func__, ret); 347 return ret; 348 } 349 350 ret = clk_enable(&pclk); 351 if (ret) { 352 debug("%s: peripheral clock enable error %d\n", __func__, ret); 353 return ret; 354 } 355 356 /* Verify pixel clock value if any & inform user accordingly */ 357 ret = clk_get_by_name(dev, "pxclk", &pxclk); 358 if (!ret) { 359 if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ) 360 printf("Warning: please adjust ltdc pixel clock\n"); 361 } 362 363 /* TODO Below parameters are hard-coded for the moment... */ 364 priv->l2bpp = VIDEO_BPP16; 365 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */ 366 priv->crop_x = 0; 367 priv->crop_y = 0; 368 priv->crop_w = priv->timing.hactive.typ; 369 priv->crop_h = priv->timing.vactive.typ; 370 priv->alpha = 0xFF; 371 372 debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__, 373 priv->timing.hactive.typ, priv->timing.vactive.typ, 374 VNBITS(priv->l2bpp), uc_plat->base); 375 debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__, 376 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h, 377 priv->bg_col_argb, priv->alpha); 378 379 /* Configure & start LTDC */ 380 stm32_ltdc_set_mode(priv); 381 stm32_ltdc_set_layer1(priv, uc_plat->base); 382 stm32_ltdc_enable(priv); 383 384 uc_priv->xsize = priv->timing.hactive.typ; 385 uc_priv->ysize = priv->timing.vactive.typ; 386 uc_priv->bpix = priv->l2bpp; 387 388 video_set_flush_dcache(dev, true); 389 390 return 0; 391 } 392 393 static int stm32_ltdc_bind(struct udevice *dev) 394 { 395 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); 396 397 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES * 398 CONFIG_VIDEO_STM32_MAX_YRES * 399 (CONFIG_VIDEO_STM32_MAX_BPP >> 3); 400 debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size); 401 402 return 0; 403 } 404 405 static const struct udevice_id stm32_ltdc_ids[] = { 406 { .compatible = "st,stm32-ltdc" }, 407 { } 408 }; 409 410 U_BOOT_DRIVER(stm32_ltdc) = { 411 .name = "stm32_ltdc", 412 .id = UCLASS_VIDEO, 413 .of_match = stm32_ltdc_ids, 414 .probe = stm32_ltdc_probe, 415 .bind = stm32_ltdc_bind, 416 .priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv), 417 }; 418