xref: /openbmc/u-boot/drivers/video/ssd2828.h (revision f77d4410)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
4  */
5 
6 /*
7  * Support for the SSD2828 bridge chip, which can take pixel data coming
8  * from a parallel LCD interface and translate it on the flight into MIPI DSI
9  * interface for driving a MIPI compatible TFT display.
10  *
11  * Implemented as a utility function. To be used from display drivers, which are
12  * responsible for driving parallel LCD hardware in front of the video pipeline.
13  */
14 
15 #ifndef _SSD2828_H
16 #define _SSD2828_H
17 
18 struct ctfb_res_modes;
19 
20 struct ssd2828_config {
21 	/*********************************************************************/
22 	/* SSD2828 configuration                                             */
23 	/*********************************************************************/
24 
25 	/*
26 	 * The pins, which are used for SPI communication. This is only used
27 	 * for configuring SSD2828, so the performance is irrelevant (only
28 	 * around a hundred of bytes is moved). Also these can be any arbitrary
29 	 * GPIO pins (not necessarily the pins having hardware SPI function).
30 	 * Moreover, the 'sdo' pin may be even not wired up in some devices.
31 	 *
32 	 * These configuration variables need to be set as pin numbers for
33 	 * the standard u-boot GPIO interface (gpio_get_value/gpio_set_value
34 	 * functions). Note that -1 value can be used for the pins, which are
35 	 * not really wired up.
36 	 */
37 	int csx_pin;
38 	int sck_pin;
39 	int sdi_pin;
40 	int sdo_pin;
41 	/* SSD2828 reset pin (shared with LCD panel reset) */
42 	int reset_pin;
43 
44 	/*
45 	 * The SSD2828 has its own dedicated clock source 'tx_clk' (connected
46 	 * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for
47 	 * clocking SPI after reset. The exact clock speed is not strictly,
48 	 * defined, but the datasheet says that it must be somewhere in the
49 	 * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
50 	 * used as a reference clock for PLL. If the exact clock frequency
51 	 * is known, then it can be specified here. If it is unknown, or the
52 	 * information is not trustworthy, then it can be set to 0.
53 	 *
54 	 * If unsure, set to 0.
55 	 */
56 	int ssd2828_tx_clk_khz;
57 
58 	/*
59 	 * This is not a property of the used LCD panel, but more like a
60 	 * property of the SSD2828 wiring. See the "SSD2828QN4 RGB data
61 	 * arrangement" table in the datasheet. The SSD2828 pins are arranged
62 	 * in such a way that 18bpp and 24bpp configurations are completely
63 	 * incompatible with each other.
64 	 *
65 	 * Depending on the color depth, this must be set to 16, 18 or 24.
66 	 */
67 	int ssd2828_color_depth;
68 
69 	/*********************************************************************/
70 	/* LCD panel configuration                                           */
71 	/*********************************************************************/
72 
73 	/*
74 	 * The number of lanes in the MIPI DSI interface. May vary from 1 to 4.
75 	 *
76 	 * This information can be found in the LCD panel datasheet.
77 	 */
78 	int mipi_dsi_number_of_data_lanes;
79 
80 	/*
81 	 * Data transfer bit rate per lane. Please note that it is expected
82 	 * to be higher than the pixel clock rate of the used video mode when
83 	 * multiplied by the number of lanes. This is perfectly normal because
84 	 * MIPI DSI handles data transfers in periodic bursts, and uses the
85 	 * idle time between bursts for sending configuration information and
86 	 * commands. Or just for saving power.
87 	 *
88 	 * The necessary Mbps/lane information can be found in the LCD panel
89 	 * datasheet. Note that the transfer rate can't be always set precisely
90 	 * and it may be rounded *up* (introducing no more than 10Mbps error).
91 	 */
92 	int mipi_dsi_bitrate_per_data_lane_mbps;
93 
94 	/*
95 	 * Setting this to 1 enforces packing of 18bpp pixel data in 24bpp
96 	 * envelope when sending it over the MIPI DSI link.
97 	 *
98 	 * If unsure, set to 0.
99 	 */
100 	int mipi_dsi_loosely_packed_pixel_format;
101 
102 	/*
103 	 * According to the "Example for system sleep in and out" section in
104 	 * the SSD2828 datasheet, some LCD panel specific delays are necessary
105 	 * after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON.
106 	 *
107 	 * For example, Allwinner uses 100 milliseconds delay after
108 	 * EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON.
109 	 */
110 	int mipi_dsi_delay_after_exit_sleep_mode_ms;
111 	int mipi_dsi_delay_after_set_display_on_ms;
112 };
113 
114 /*
115  * Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure
116  * and also the video mode timings.
117  *
118  * The right place to insert this function call is after the parallel LCD
119  * interface is initialized and before turning on the backlight. This is
120  * advised in the "Example for system sleep in and out" section of the
121  * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source
122  * for PLL, which means that the input signal must be already there.
123  */
124 int ssd2828_init(const struct ssd2828_config *cfg,
125 		 const struct ctfb_res_modes *mode);
126 
127 #endif
128