1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * Author: Donghwa Lee <dh09.lee@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/mipi_dsim.h> 11 12 #include "exynos/exynos_mipi_dsi_lowlevel.h" 13 #include "exynos/exynos_mipi_dsi_common.h" 14 15 static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) 16 { 17 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 18 int reverse = dsim_dev->dsim_lcd_dev->reverse_panel; 19 static const unsigned char data_to_send[] = { 20 0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c, 21 0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20, 22 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, 23 0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3, 24 0xff, 0xff, 0xc8 25 }; 26 27 static const unsigned char data_to_send_reverse[] = { 28 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c, 29 0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20, 30 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, 31 0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1, 32 0xf6, 0xf6, 0xc1 33 }; 34 35 if (reverse) { 36 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 37 data_to_send_reverse, 38 ARRAY_SIZE(data_to_send_reverse)); 39 } else { 40 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 41 data_to_send, ARRAY_SIZE(data_to_send)); 42 } 43 } 44 45 static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) 46 { 47 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 48 static const unsigned char data_to_send[] = { 49 0xf2, 0x80, 0x03, 0x0d 50 }; 51 52 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 53 data_to_send, ARRAY_SIZE(data_to_send)); 54 } 55 56 static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) 57 { 58 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 59 /* 7500K 2.2 Set : 30cd */ 60 static const unsigned char data_to_send[] = { 61 0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad, 62 0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1, 63 0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74, 64 }; 65 66 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 67 data_to_send, ARRAY_SIZE(data_to_send)); 68 } 69 70 static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) 71 { 72 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 73 static const unsigned char data_to_send[] = { 74 0xf7, 0x03 75 }; 76 77 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, 78 ARRAY_SIZE(data_to_send)); 79 } 80 81 static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) 82 { 83 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 84 static const unsigned char data_to_send[] = { 85 0xf6, 0x00, 0x02, 0x00 86 }; 87 88 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 89 data_to_send, ARRAY_SIZE(data_to_send)); 90 } 91 92 static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) 93 { 94 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 95 static const unsigned char data_to_send[] = { 96 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, 97 0x00 98 }; 99 100 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 101 data_to_send, ARRAY_SIZE(data_to_send)); 102 } 103 104 static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) 105 { 106 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 107 static const unsigned char data_to_send[] = { 108 0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d 109 }; 110 111 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 112 data_to_send, ARRAY_SIZE(data_to_send)); 113 } 114 115 static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) 116 { 117 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 118 static const unsigned char data_to_send[] = { 119 0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03 120 }; 121 122 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 123 data_to_send, ARRAY_SIZE(data_to_send)); 124 } 125 126 static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) 127 { 128 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 129 static const unsigned char data_to_send[] = { 130 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02 131 }; 132 133 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 134 data_to_send, ARRAY_SIZE(data_to_send)); 135 } 136 137 static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) 138 { 139 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 140 static const unsigned char data_to_send[] = { 141 0xe3, 0x40 142 }; 143 144 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, 145 ARRAY_SIZE(data_to_send)); 146 } 147 148 static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) 149 { 150 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 151 static const unsigned char data_to_send[] = { 152 0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00 153 }; 154 155 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 156 data_to_send, ARRAY_SIZE(data_to_send)); 157 } 158 159 static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) 160 { 161 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 162 static const unsigned char data_to_send[] = { 163 0xb1, 0x04, 0x00 164 }; 165 166 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 167 data_to_send, ARRAY_SIZE(data_to_send)); 168 } 169 170 static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) 171 { 172 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 173 static const unsigned char data_to_send[] = { 174 0x29, 0x00 175 }; 176 177 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, 178 ARRAY_SIZE(data_to_send)); 179 } 180 181 static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) 182 { 183 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 184 static const unsigned char data_to_send[] = { 185 0x11, 0x00 186 }; 187 188 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, 189 ARRAY_SIZE(data_to_send)); 190 } 191 192 static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) 193 { 194 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 195 static const unsigned char data_to_send[] = { 196 0xf0, 0x5a, 0x5a 197 }; 198 199 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 200 data_to_send, ARRAY_SIZE(data_to_send)); 201 } 202 203 static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) 204 { 205 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; 206 static const unsigned char data_to_send[] = { 207 0xf1, 0x5a, 0x5a 208 }; 209 210 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, 211 data_to_send, ARRAY_SIZE(data_to_send)); 212 } 213 214 static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) 215 { 216 /* 217 * in case of setting gamma and panel condition at first, 218 * it shuold be setting like below. 219 * set_gamma() -> set_panel_condition() 220 */ 221 222 s6e8ax0_apply_level1_key(dsim_dev); 223 s6e8ax0_apply_mtp_key(dsim_dev); 224 225 s6e8ax0_sleep_out(dsim_dev); 226 mdelay(5); 227 s6e8ax0_panel_cond(dsim_dev); 228 s6e8ax0_display_cond(dsim_dev); 229 s6e8ax0_gamma_cond(dsim_dev); 230 s6e8ax0_gamma_update(dsim_dev); 231 232 s6e8ax0_etc_source_control(dsim_dev); 233 s6e8ax0_elvss_set(dsim_dev); 234 s6e8ax0_etc_pentile_control(dsim_dev); 235 s6e8ax0_etc_mipi_control1(dsim_dev); 236 s6e8ax0_etc_mipi_control2(dsim_dev); 237 s6e8ax0_etc_power_control(dsim_dev); 238 s6e8ax0_etc_mipi_control3(dsim_dev); 239 s6e8ax0_etc_mipi_control4(dsim_dev); 240 } 241 242 static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev) 243 { 244 s6e8ax0_panel_init(dsim_dev); 245 246 return 0; 247 } 248 249 static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev) 250 { 251 s6e8ax0_display_on(dsim_dev); 252 } 253 254 static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = { 255 .name = "s6e8ax0", 256 .id = -1, 257 258 .mipi_panel_init = s6e8ax0_panel_set, 259 .mipi_display_on = s6e8ax0_display_enable, 260 }; 261 262 void s6e8ax0_init(void) 263 { 264 exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver); 265 } 266