1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <edid.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <video.h> 16 #include <asm/gpio.h> 17 #include <asm/hardware.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/cru_rk3288.h> 21 #include <asm/arch/grf_rk3288.h> 22 #include <asm/arch/edp_rk3288.h> 23 #include <asm/arch/vop_rk3288.h> 24 #include <dm/device-internal.h> 25 #include <dm/uclass-internal.h> 26 #include <dt-bindings/clock/rk3288-cru.h> 27 #include <power/regulator.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 struct rk_vop_priv { 32 struct rk3288_vop *regs; 33 struct rk3288_grf *grf; 34 }; 35 36 void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, 37 int fb_bits_per_pixel, const struct display_timing *edid) 38 { 39 u32 lb_mode; 40 u32 rgb_mode; 41 u32 hactive = edid->hactive.typ; 42 u32 vactive = edid->vactive.typ; 43 44 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), 45 ®s->win0_act_info); 46 47 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | 48 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), 49 ®s->win0_dsp_st); 50 51 writel(V_DSP_WIDTH(hactive - 1) | 52 V_DSP_HEIGHT(vactive - 1), 53 ®s->win0_dsp_info); 54 55 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, 56 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); 57 58 switch (fb_bits_per_pixel) { 59 case 16: 60 rgb_mode = RGB565; 61 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir); 62 break; 63 case 24: 64 rgb_mode = RGB888; 65 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir); 66 break; 67 case 32: 68 default: 69 rgb_mode = ARGB8888; 70 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir); 71 break; 72 } 73 74 if (hactive > 2560) 75 lb_mode = LB_RGB_3840X2; 76 else if (hactive > 1920) 77 lb_mode = LB_RGB_2560X4; 78 else if (hactive > 1280) 79 lb_mode = LB_RGB_1920X5; 80 else 81 lb_mode = LB_RGB_1280X8; 82 83 clrsetbits_le32(®s->win0_ctrl0, 84 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, 85 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | 86 V_WIN0_EN(1)); 87 88 writel(fbbase, ®s->win0_yrgb_mst); 89 writel(0x01, ®s->reg_cfg_done); /* enable reg config */ 90 } 91 92 void rkvop_mode_set(struct rk3288_vop *regs, 93 const struct display_timing *edid, enum vop_modes mode) 94 { 95 u32 hactive = edid->hactive.typ; 96 u32 vactive = edid->vactive.typ; 97 u32 hsync_len = edid->hsync_len.typ; 98 u32 hback_porch = edid->hback_porch.typ; 99 u32 vsync_len = edid->vsync_len.typ; 100 u32 vback_porch = edid->vback_porch.typ; 101 u32 hfront_porch = edid->hfront_porch.typ; 102 u32 vfront_porch = edid->vfront_porch.typ; 103 uint flags; 104 int mode_flags; 105 106 switch (mode) { 107 case VOP_MODE_HDMI: 108 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 109 V_HDMI_OUT_EN(1)); 110 break; 111 case VOP_MODE_EDP: 112 default: 113 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 114 V_EDP_OUT_EN(1)); 115 break; 116 case VOP_MODE_LVDS: 117 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 118 V_RGB_OUT_EN(1)); 119 break; 120 } 121 122 if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP) 123 /* RGBaaa */ 124 mode_flags = 15; 125 else 126 /* RGB888 */ 127 mode_flags = 0; 128 129 flags = V_DSP_OUT_MODE(mode_flags) | 130 V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) | 131 V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)); 132 133 clrsetbits_le32(®s->dsp_ctrl0, 134 M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, 135 flags); 136 137 writel(V_HSYNC(hsync_len) | 138 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), 139 ®s->dsp_htotal_hs_end); 140 141 writel(V_HEAP(hsync_len + hback_porch + hactive) | 142 V_HASP(hsync_len + hback_porch), 143 ®s->dsp_hact_st_end); 144 145 writel(V_VSYNC(vsync_len) | 146 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), 147 ®s->dsp_vtotal_vs_end); 148 149 writel(V_VAEP(vsync_len + vback_porch + vactive)| 150 V_VASP(vsync_len + vback_porch), 151 ®s->dsp_vact_st_end); 152 153 writel(V_HEAP(hsync_len + hback_porch + hactive) | 154 V_HASP(hsync_len + hback_porch), 155 ®s->post_dsp_hact_info); 156 157 writel(V_VAEP(vsync_len + vback_porch + vactive)| 158 V_VASP(vsync_len + vback_porch), 159 ®s->post_dsp_vact_info); 160 161 writel(0x01, ®s->reg_cfg_done); /* enable reg config */ 162 } 163 164 /** 165 * rk_display_init() - Try to enable the given display device 166 * 167 * This function performs many steps: 168 * - Finds the display device being referenced by @ep_node 169 * - Puts the VOP's ID into its uclass platform data 170 * - Probes the device to set it up 171 * - Reads the EDID timing information 172 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode 173 * - Enables the display (the display device handles this and will do different 174 * things depending on the display type) 175 * - Tells the uclass about the display resolution so that the console will 176 * appear correctly 177 * 178 * @dev: VOP device that we want to connect to the display 179 * @fbbase: Frame buffer address 180 * @l2bpp Log2 of bits-per-pixels for the display 181 * @ep_node: Device tree node to process - this is the offset of an endpoint 182 * node within the VOP's 'port' list. 183 * @return 0 if OK, -ve if something went wrong 184 */ 185 int rk_display_init(struct udevice *dev, ulong fbbase, 186 enum video_log2_bpp l2bpp, int ep_node) 187 { 188 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 189 const void *blob = gd->fdt_blob; 190 struct rk_vop_priv *priv = dev_get_priv(dev); 191 int vop_id, remote_vop_id; 192 struct rk3288_vop *regs = priv->regs; 193 struct display_timing timing; 194 struct udevice *disp; 195 int ret, remote, i, offset; 196 struct display_plat *disp_uc_plat; 197 struct clk clk; 198 199 vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); 200 debug("vop_id=%d\n", vop_id); 201 remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint"); 202 if (remote < 0) 203 return -EINVAL; 204 remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1); 205 debug("remote vop_id=%d\n", remote_vop_id); 206 207 for (i = 0, offset = remote; i < 3 && offset > 0; i++) 208 offset = fdt_parent_offset(blob, offset); 209 if (offset < 0) { 210 debug("%s: Invalid remote-endpoint position\n", dev->name); 211 return -EINVAL; 212 } 213 214 ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp); 215 if (ret) { 216 debug("%s: device '%s' display not found (ret=%d)\n", __func__, 217 dev->name, ret); 218 return ret; 219 } 220 221 disp_uc_plat = dev_get_uclass_platdata(disp); 222 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); 223 if (display_in_use(disp)) { 224 debug(" - device in use\n"); 225 return -EBUSY; 226 } 227 228 disp_uc_plat->source_id = remote_vop_id; 229 disp_uc_plat->src_dev = dev; 230 231 ret = device_probe(disp); 232 if (ret) { 233 debug("%s: device '%s' display won't probe (ret=%d)\n", 234 __func__, dev->name, ret); 235 return ret; 236 } 237 238 ret = display_read_timing(disp, &timing); 239 if (ret) { 240 debug("%s: Failed to read timings\n", __func__); 241 return ret; 242 } 243 244 ret = clk_get_by_index(dev, 1, &clk); 245 if (!ret) 246 ret = clk_set_rate(&clk, timing.pixelclock.typ); 247 if (ret) { 248 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret); 249 return ret; 250 } 251 252 rkvop_mode_set(regs, &timing, vop_id); 253 254 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); 255 256 ret = display_enable(disp, 1 << l2bpp, &timing); 257 if (ret) 258 return ret; 259 260 uc_priv->xsize = timing.hactive.typ; 261 uc_priv->ysize = timing.vactive.typ; 262 uc_priv->bpix = l2bpp; 263 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize); 264 265 return 0; 266 } 267 268 static int rk_vop_probe(struct udevice *dev) 269 { 270 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 271 const void *blob = gd->fdt_blob; 272 struct rk_vop_priv *priv = dev_get_priv(dev); 273 struct udevice *reg; 274 int ret, port, node; 275 276 /* Before relocation we don't need to do anything */ 277 if (!(gd->flags & GD_FLG_RELOC)) 278 return 0; 279 280 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 281 priv->regs = (struct rk3288_vop *)dev_get_addr(dev); 282 283 /* lcdc(vop) iodomain select 1.8V */ 284 rk_setreg(&priv->grf->io_vsel, 1 << 0); 285 286 /* 287 * Try some common regulators. We should really get these from the 288 * device tree somehow. 289 */ 290 ret = regulator_autoset_by_name("vcc18_lcd", ®); 291 if (ret) 292 debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__); 293 ret = regulator_autoset_by_name("VCC18_LCD", ®); 294 if (ret) 295 debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__); 296 ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", ®); 297 if (ret) { 298 debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n", 299 __func__); 300 } 301 ret = regulator_autoset_by_name("vdd10_lcd", ®); 302 if (ret) { 303 debug("%s: Cannot autoset regulator vdd10_lcd\n", 304 __func__); 305 } 306 ret = regulator_autoset_by_name("VDD10_LCD", ®); 307 if (ret) { 308 debug("%s: Cannot autoset regulator VDD10_LCD\n", 309 __func__); 310 } 311 ret = regulator_autoset_by_name("vcc33_lcd", ®); 312 if (ret) 313 debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__); 314 315 /* 316 * Try all the ports until we find one that works. In practice this 317 * tries EDP first if available, then HDMI. 318 * 319 * Note that rockchip_vop_set_clk() always uses NPLL as the source 320 * clock so it is currently not possible to use more than one display 321 * device simultaneously. 322 */ 323 port = fdt_subnode_offset(blob, dev_of_offset(dev), "port"); 324 if (port < 0) 325 return -EINVAL; 326 for (node = fdt_first_subnode(blob, port); 327 node > 0; 328 node = fdt_next_subnode(blob, node)) { 329 ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node); 330 if (ret) 331 debug("Device failed: ret=%d\n", ret); 332 if (!ret) 333 break; 334 } 335 video_set_flush_dcache(dev, 1); 336 337 return ret; 338 } 339 340 static int rk_vop_bind(struct udevice *dev) 341 { 342 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 343 344 plat->size = 1920 * 1080 * 2; 345 346 return 0; 347 } 348 349 static const struct video_ops rk_vop_ops = { 350 }; 351 352 static const struct udevice_id rk_vop_ids[] = { 353 { .compatible = "rockchip,rk3288-vop" }, 354 { } 355 }; 356 357 U_BOOT_DRIVER(rk_vop) = { 358 .name = "rk_vop", 359 .id = UCLASS_VIDEO, 360 .of_match = rk_vop_ids, 361 .ops = &rk_vop_ops, 362 .bind = rk_vop_bind, 363 .probe = rk_vop_probe, 364 .priv_auto_alloc_size = sizeof(struct rk_vop_priv), 365 }; 366