1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <edid.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <video.h> 16 #include <asm/gpio.h> 17 #include <asm/hardware.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/edp_rk3288.h> 21 #include <asm/arch/vop_rk3288.h> 22 #include <dm/device-internal.h> 23 #include <dm/uclass-internal.h> 24 #include <power/regulator.h> 25 #include "rk_vop.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 enum vop_pol { 30 HSYNC_POSITIVE = 0, 31 VSYNC_POSITIVE = 1, 32 DEN_NEGATIVE = 2, 33 DCLK_INVERT = 3 34 }; 35 36 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, 37 int fb_bits_per_pixel, 38 const struct display_timing *edid) 39 { 40 u32 lb_mode; 41 u32 rgb_mode; 42 u32 hactive = edid->hactive.typ; 43 u32 vactive = edid->vactive.typ; 44 45 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), 46 ®s->win0_act_info); 47 48 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | 49 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), 50 ®s->win0_dsp_st); 51 52 writel(V_DSP_WIDTH(hactive - 1) | 53 V_DSP_HEIGHT(vactive - 1), 54 ®s->win0_dsp_info); 55 56 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, 57 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); 58 59 switch (fb_bits_per_pixel) { 60 case 16: 61 rgb_mode = RGB565; 62 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir); 63 break; 64 case 24: 65 rgb_mode = RGB888; 66 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir); 67 break; 68 case 32: 69 default: 70 rgb_mode = ARGB8888; 71 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir); 72 break; 73 } 74 75 if (hactive > 2560) 76 lb_mode = LB_RGB_3840X2; 77 else if (hactive > 1920) 78 lb_mode = LB_RGB_2560X4; 79 else if (hactive > 1280) 80 lb_mode = LB_RGB_1920X5; 81 else 82 lb_mode = LB_RGB_1280X8; 83 84 clrsetbits_le32(®s->win0_ctrl0, 85 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, 86 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | 87 V_WIN0_EN(1)); 88 89 writel(fbbase, ®s->win0_yrgb_mst); 90 writel(0x01, ®s->reg_cfg_done); /* enable reg config */ 91 } 92 93 static void rkvop_set_pin_polarity(struct udevice *dev, 94 enum vop_modes mode, u32 polarity) 95 { 96 struct rkvop_driverdata *ops = 97 (struct rkvop_driverdata *)dev_get_driver_data(dev); 98 99 if (ops->set_pin_polarity) 100 ops->set_pin_polarity(dev, mode, polarity); 101 } 102 103 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) 104 { 105 struct rk_vop_priv *priv = dev_get_priv(dev); 106 struct rk3288_vop *regs = priv->regs; 107 108 switch (mode) { 109 case VOP_MODE_HDMI: 110 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 111 V_HDMI_OUT_EN(1)); 112 break; 113 114 case VOP_MODE_EDP: 115 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 116 V_EDP_OUT_EN(1)); 117 break; 118 119 case VOP_MODE_LVDS: 120 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 121 V_RGB_OUT_EN(1)); 122 break; 123 124 case VOP_MODE_MIPI: 125 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 126 V_MIPI_OUT_EN(1)); 127 break; 128 129 default: 130 debug("%s: unsupported output mode %x\n", __func__, mode); 131 } 132 } 133 134 static void rkvop_mode_set(struct udevice *dev, 135 const struct display_timing *edid, 136 enum vop_modes mode) 137 { 138 struct rk_vop_priv *priv = dev_get_priv(dev); 139 struct rk3288_vop *regs = priv->regs; 140 struct rkvop_driverdata *data = 141 (struct rkvop_driverdata *)dev_get_driver_data(dev); 142 143 u32 hactive = edid->hactive.typ; 144 u32 vactive = edid->vactive.typ; 145 u32 hsync_len = edid->hsync_len.typ; 146 u32 hback_porch = edid->hback_porch.typ; 147 u32 vsync_len = edid->vsync_len.typ; 148 u32 vback_porch = edid->vback_porch.typ; 149 u32 hfront_porch = edid->hfront_porch.typ; 150 u32 vfront_porch = edid->vfront_porch.typ; 151 int mode_flags; 152 u32 pin_polarity; 153 154 pin_polarity = BIT(DCLK_INVERT); 155 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) 156 pin_polarity |= BIT(HSYNC_POSITIVE); 157 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH) 158 pin_polarity |= BIT(VSYNC_POSITIVE); 159 160 rkvop_set_pin_polarity(dev, mode, pin_polarity); 161 rkvop_enable_output(dev, mode); 162 163 mode_flags = 0; /* RGB888 */ 164 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) && 165 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)) 166 mode_flags = 15; /* RGBaaa */ 167 168 clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE, 169 V_DSP_OUT_MODE(mode_flags)); 170 171 writel(V_HSYNC(hsync_len) | 172 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), 173 ®s->dsp_htotal_hs_end); 174 175 writel(V_HEAP(hsync_len + hback_porch + hactive) | 176 V_HASP(hsync_len + hback_porch), 177 ®s->dsp_hact_st_end); 178 179 writel(V_VSYNC(vsync_len) | 180 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), 181 ®s->dsp_vtotal_vs_end); 182 183 writel(V_VAEP(vsync_len + vback_porch + vactive)| 184 V_VASP(vsync_len + vback_porch), 185 ®s->dsp_vact_st_end); 186 187 writel(V_HEAP(hsync_len + hback_porch + hactive) | 188 V_HASP(hsync_len + hback_porch), 189 ®s->post_dsp_hact_info); 190 191 writel(V_VAEP(vsync_len + vback_porch + vactive)| 192 V_VASP(vsync_len + vback_porch), 193 ®s->post_dsp_vact_info); 194 195 writel(0x01, ®s->reg_cfg_done); /* enable reg config */ 196 } 197 198 /** 199 * rk_display_init() - Try to enable the given display device 200 * 201 * This function performs many steps: 202 * - Finds the display device being referenced by @ep_node 203 * - Puts the VOP's ID into its uclass platform data 204 * - Probes the device to set it up 205 * - Reads the EDID timing information 206 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode 207 * - Enables the display (the display device handles this and will do different 208 * things depending on the display type) 209 * - Tells the uclass about the display resolution so that the console will 210 * appear correctly 211 * 212 * @dev: VOP device that we want to connect to the display 213 * @fbbase: Frame buffer address 214 * @ep_node: Device tree node to process - this is the offset of an endpoint 215 * node within the VOP's 'port' list. 216 * @return 0 if OK, -ve if something went wrong 217 */ 218 static int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) 219 { 220 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 221 const void *blob = gd->fdt_blob; 222 struct rk_vop_priv *priv = dev_get_priv(dev); 223 int vop_id, remote_vop_id; 224 struct rk3288_vop *regs = priv->regs; 225 struct display_timing timing; 226 struct udevice *disp; 227 int ret, remote, i, offset; 228 struct display_plat *disp_uc_plat; 229 struct clk clk; 230 enum video_log2_bpp l2bpp; 231 232 vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); 233 debug("vop_id=%d\n", vop_id); 234 remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint"); 235 if (remote < 0) 236 return -EINVAL; 237 remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1); 238 debug("remote vop_id=%d\n", remote_vop_id); 239 240 for (i = 0, offset = remote; i < 3 && offset > 0; i++) 241 offset = fdt_parent_offset(blob, offset); 242 if (offset < 0) { 243 debug("%s: Invalid remote-endpoint position\n", dev->name); 244 return -EINVAL; 245 } 246 247 ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp); 248 if (ret) { 249 debug("%s: device '%s' display not found (ret=%d)\n", __func__, 250 dev->name, ret); 251 return ret; 252 } 253 254 disp_uc_plat = dev_get_uclass_platdata(disp); 255 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); 256 if (display_in_use(disp)) { 257 debug(" - device in use\n"); 258 return -EBUSY; 259 } 260 261 disp_uc_plat->source_id = remote_vop_id; 262 disp_uc_plat->src_dev = dev; 263 264 ret = device_probe(disp); 265 if (ret) { 266 debug("%s: device '%s' display won't probe (ret=%d)\n", 267 __func__, dev->name, ret); 268 return ret; 269 } 270 271 ret = display_read_timing(disp, &timing); 272 if (ret) { 273 debug("%s: Failed to read timings\n", __func__); 274 return ret; 275 } 276 277 ret = clk_get_by_index(dev, 1, &clk); 278 if (!ret) 279 ret = clk_set_rate(&clk, timing.pixelclock.typ); 280 if (IS_ERR_VALUE(ret)) { 281 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret); 282 return ret; 283 } 284 285 /* Set bitwidth for vop display according to vop mode */ 286 switch (vop_id) { 287 case VOP_MODE_EDP: 288 case VOP_MODE_LVDS: 289 l2bpp = VIDEO_BPP16; 290 break; 291 case VOP_MODE_HDMI: 292 case VOP_MODE_MIPI: 293 l2bpp = VIDEO_BPP32; 294 break; 295 default: 296 l2bpp = VIDEO_BPP16; 297 } 298 299 rkvop_mode_set(dev, &timing, vop_id); 300 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); 301 302 ret = display_enable(disp, 1 << l2bpp, &timing); 303 if (ret) 304 return ret; 305 306 uc_priv->xsize = timing.hactive.typ; 307 uc_priv->ysize = timing.vactive.typ; 308 uc_priv->bpix = l2bpp; 309 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize); 310 311 return 0; 312 } 313 314 void rk_vop_probe_regulators(struct udevice *dev, 315 const char * const *names, int cnt) 316 { 317 int i, ret; 318 const char *name; 319 struct udevice *reg; 320 321 for (i = 0; i < cnt; ++i) { 322 name = names[i]; 323 debug("%s: probing regulator '%s'\n", dev->name, name); 324 325 ret = regulator_autoset_by_name(name, ®); 326 if (!ret) 327 ret = regulator_set_enable(reg, true); 328 } 329 } 330 331 int rk_vop_probe(struct udevice *dev) 332 { 333 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 334 const void *blob = gd->fdt_blob; 335 struct rk_vop_priv *priv = dev_get_priv(dev); 336 int ret = 0; 337 int port, node; 338 339 /* Before relocation we don't need to do anything */ 340 if (!(gd->flags & GD_FLG_RELOC)) 341 return 0; 342 343 priv->regs = (struct rk3288_vop *)devfdt_get_addr(dev); 344 345 /* 346 * Try all the ports until we find one that works. In practice this 347 * tries EDP first if available, then HDMI. 348 * 349 * Note that rockchip_vop_set_clk() always uses NPLL as the source 350 * clock so it is currently not possible to use more than one display 351 * device simultaneously. 352 */ 353 port = fdt_subnode_offset(blob, dev_of_offset(dev), "port"); 354 if (port < 0) 355 return -EINVAL; 356 for (node = fdt_first_subnode(blob, port); 357 node > 0; 358 node = fdt_next_subnode(blob, node)) { 359 ret = rk_display_init(dev, plat->base, node); 360 if (ret) 361 debug("Device failed: ret=%d\n", ret); 362 if (!ret) 363 break; 364 } 365 video_set_flush_dcache(dev, 1); 366 367 return ret; 368 } 369 370 int rk_vop_bind(struct udevice *dev) 371 { 372 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 373 374 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES * 375 CONFIG_VIDEO_ROCKCHIP_MAX_YRES); 376 377 return 0; 378 } 379