1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <edid.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <video.h> 16 #include <asm/gpio.h> 17 #include <asm/hardware.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/cru_rk3288.h> 21 #include <asm/arch/grf_rk3288.h> 22 #include <asm/arch/edp_rk3288.h> 23 #include <asm/arch/hdmi_rk3288.h> 24 #include <asm/arch/vop_rk3288.h> 25 #include <dm/device-internal.h> 26 #include <dm/uclass-internal.h> 27 #include <dt-bindings/clock/rk3288-cru.h> 28 #include <power/regulator.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 struct rk_vop_priv { 33 struct rk3288_vop *regs; 34 struct rk3288_grf *grf; 35 }; 36 37 void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, 38 int fb_bits_per_pixel, const struct display_timing *edid) 39 { 40 u32 lb_mode; 41 u32 rgb_mode; 42 u32 hactive = edid->hactive.typ; 43 u32 vactive = edid->vactive.typ; 44 45 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1), 46 ®s->win0_act_info); 47 48 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | 49 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), 50 ®s->win0_dsp_st); 51 52 writel(V_DSP_WIDTH(hactive - 1) | 53 V_DSP_HEIGHT(vactive - 1), 54 ®s->win0_dsp_info); 55 56 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, 57 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); 58 59 switch (fb_bits_per_pixel) { 60 case 16: 61 rgb_mode = RGB565; 62 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir); 63 break; 64 case 24: 65 rgb_mode = RGB888; 66 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir); 67 break; 68 case 32: 69 default: 70 rgb_mode = ARGB8888; 71 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir); 72 break; 73 } 74 75 if (hactive > 2560) 76 lb_mode = LB_RGB_3840X2; 77 else if (hactive > 1920) 78 lb_mode = LB_RGB_2560X4; 79 else if (hactive > 1280) 80 lb_mode = LB_RGB_1920X5; 81 else 82 lb_mode = LB_RGB_1280X8; 83 84 clrsetbits_le32(®s->win0_ctrl0, 85 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, 86 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | 87 V_WIN0_EN(1)); 88 89 writel(fbbase, ®s->win0_yrgb_mst); 90 writel(0x01, ®s->reg_cfg_done); /* enable reg config */ 91 } 92 93 void rkvop_mode_set(struct rk3288_vop *regs, 94 const struct display_timing *edid, enum vop_modes mode) 95 { 96 u32 hactive = edid->hactive.typ; 97 u32 vactive = edid->vactive.typ; 98 u32 hsync_len = edid->hsync_len.typ; 99 u32 hback_porch = edid->hback_porch.typ; 100 u32 vsync_len = edid->vsync_len.typ; 101 u32 vback_porch = edid->vback_porch.typ; 102 u32 hfront_porch = edid->hfront_porch.typ; 103 u32 vfront_porch = edid->vfront_porch.typ; 104 uint flags; 105 106 switch (mode) { 107 case VOP_MODE_HDMI: 108 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 109 V_HDMI_OUT_EN(1)); 110 break; 111 case VOP_MODE_EDP: 112 default: 113 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, 114 V_EDP_OUT_EN(1)); 115 break; 116 } 117 118 flags = V_DSP_OUT_MODE(15) | 119 V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) | 120 V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)); 121 122 clrsetbits_le32(®s->dsp_ctrl0, 123 M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, 124 flags); 125 126 writel(V_HSYNC(hsync_len) | 127 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), 128 ®s->dsp_htotal_hs_end); 129 130 writel(V_HEAP(hsync_len + hback_porch + hactive) | 131 V_HASP(hsync_len + hback_porch), 132 ®s->dsp_hact_st_end); 133 134 writel(V_VSYNC(vsync_len) | 135 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), 136 ®s->dsp_vtotal_vs_end); 137 138 writel(V_VAEP(vsync_len + vback_porch + vactive)| 139 V_VASP(vsync_len + vback_porch), 140 ®s->dsp_vact_st_end); 141 142 writel(V_HEAP(hsync_len + hback_porch + hactive) | 143 V_HASP(hsync_len + hback_porch), 144 ®s->post_dsp_hact_info); 145 146 writel(V_VAEP(vsync_len + vback_porch + vactive)| 147 V_VASP(vsync_len + vback_porch), 148 ®s->post_dsp_vact_info); 149 150 writel(0x01, ®s->reg_cfg_done); /* enable reg config */ 151 } 152 153 /** 154 * rk_display_init() - Try to enable the given display device 155 * 156 * This function performs many steps: 157 * - Finds the display device being referenced by @ep_node 158 * - Puts the VOP's ID into its uclass platform data 159 * - Probes the device to set it up 160 * - Reads the EDID timing information 161 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode 162 * - Enables the display (the display device handles this and will do different 163 * things depending on the display type) 164 * - Tells the uclass about the display resolution so that the console will 165 * appear correctly 166 * 167 * @dev: VOP device that we want to connect to the display 168 * @fbbase: Frame buffer address 169 * @l2bpp Log2 of bits-per-pixels for the display 170 * @ep_node: Device tree node to process - this is the offset of an endpoint 171 * node within the VOP's 'port' list. 172 * @return 0 if OK, -ve if something went wrong 173 */ 174 int rk_display_init(struct udevice *dev, ulong fbbase, 175 enum video_log2_bpp l2bpp, int ep_node) 176 { 177 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 178 const void *blob = gd->fdt_blob; 179 struct rk_vop_priv *priv = dev_get_priv(dev); 180 int vop_id, remote_vop_id; 181 struct rk3288_vop *regs = priv->regs; 182 struct display_timing timing; 183 struct udevice *disp; 184 int ret, remote, i, offset; 185 struct display_plat *disp_uc_plat; 186 struct udevice *clk; 187 188 vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); 189 debug("vop_id=%d\n", vop_id); 190 remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint"); 191 if (remote < 0) 192 return -EINVAL; 193 remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1); 194 debug("remote vop_id=%d\n", remote_vop_id); 195 196 for (i = 0, offset = remote; i < 3 && offset > 0; i++) 197 offset = fdt_parent_offset(blob, offset); 198 if (offset < 0) { 199 debug("%s: Invalid remote-endpoint position\n", dev->name); 200 return -EINVAL; 201 } 202 203 ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp); 204 if (ret) { 205 debug("%s: device '%s' display not found (ret=%d)\n", __func__, 206 dev->name, ret); 207 return ret; 208 } 209 210 disp_uc_plat = dev_get_uclass_platdata(disp); 211 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); 212 disp_uc_plat->source_id = remote_vop_id; 213 disp_uc_plat->src_dev = dev; 214 215 ret = device_probe(disp); 216 if (ret) { 217 debug("%s: device '%s' display won't probe (ret=%d)\n", 218 __func__, dev->name, ret); 219 return ret; 220 } 221 222 ret = display_read_timing(disp, &timing); 223 if (ret) { 224 debug("%s: Failed to read timings\n", __func__); 225 return ret; 226 } 227 228 ret = rkclk_get_clk(CLK_NEW, &clk); 229 if (!ret) { 230 ret = clk_set_periph_rate(clk, DCLK_VOP0 + vop_id, 231 timing.pixelclock.typ); 232 } 233 if (ret) { 234 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret); 235 return ret; 236 } 237 238 rkvop_mode_set(regs, &timing, vop_id); 239 240 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); 241 242 ret = display_enable(disp, 1 << l2bpp, &timing); 243 if (ret) 244 return ret; 245 246 uc_priv->xsize = timing.hactive.typ; 247 uc_priv->ysize = timing.vactive.typ; 248 uc_priv->bpix = l2bpp; 249 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize); 250 251 return 0; 252 } 253 254 static int rk_vop_probe(struct udevice *dev) 255 { 256 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 257 const void *blob = gd->fdt_blob; 258 struct rk_vop_priv *priv = dev_get_priv(dev); 259 struct udevice *reg; 260 int ret, port, node; 261 262 /* Before relocation we don't need to do anything */ 263 if (!(gd->flags & GD_FLG_RELOC)) 264 return 0; 265 266 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 267 priv->regs = (struct rk3288_vop *)dev_get_addr(dev); 268 269 /* lcdc(vop) iodomain select 1.8V */ 270 rk_setreg(&priv->grf->io_vsel, 1 << 0); 271 272 /* 273 * Try some common regulators. We should really get these from the 274 * device tree somehow. 275 */ 276 ret = regulator_autoset_by_name("vcc18_lcd", ®); 277 if (ret) 278 debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__); 279 ret = regulator_autoset_by_name("VCC18_LCD", ®); 280 if (ret) 281 debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__); 282 ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", ®); 283 if (ret) { 284 debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n", 285 __func__); 286 } 287 ret = regulator_autoset_by_name("vdd10_lcd", ®); 288 if (ret) { 289 debug("%s: Cannot autoset regulator vdd10_lcd\n", 290 __func__); 291 } 292 ret = regulator_autoset_by_name("VDD10_LCD", ®); 293 if (ret) { 294 debug("%s: Cannot autoset regulator VDD10_LCD\n", 295 __func__); 296 } 297 ret = regulator_autoset_by_name("vcc33_lcd", ®); 298 if (ret) 299 debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__); 300 301 /* 302 * Try all the ports until we find one that works. In practice this 303 * tries EDP first if available, then HDMI. 304 */ 305 port = fdt_subnode_offset(blob, dev->of_offset, "port"); 306 if (port < 0) 307 return -EINVAL; 308 for (node = fdt_first_subnode(blob, port); 309 node > 0; 310 node = fdt_next_subnode(blob, node)) { 311 ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node); 312 if (ret) 313 debug("Device failed: ret=%d\n", ret); 314 if (!ret) 315 break; 316 } 317 318 return ret; 319 } 320 321 static int rk_vop_bind(struct udevice *dev) 322 { 323 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 324 325 plat->size = 1920 * 1080 * 2; 326 327 return 0; 328 } 329 330 static const struct video_ops rk_vop_ops = { 331 }; 332 333 static const struct udevice_id rk_vop_ids[] = { 334 { .compatible = "rockchip,rk3288-vop" }, 335 { } 336 }; 337 338 U_BOOT_DRIVER(rk_vop) = { 339 .name = "rk_vop", 340 .id = UCLASS_VIDEO, 341 .of_match = rk_vop_ids, 342 .ops = &rk_vop_ops, 343 .bind = rk_vop_bind, 344 .probe = rk_vop_probe, 345 .priv_auto_alloc_size = sizeof(struct rk_vop_priv), 346 }; 347