1*36602ebaSeric.gao@rock-chips.com /* 2*36602ebaSeric.gao@rock-chips.com * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd 3*36602ebaSeric.gao@rock-chips.com * Author: Eric Gao <eric.gao@rock-chips.com> 4*36602ebaSeric.gao@rock-chips.com * SPDX-License-Identifier: GPL-2.0+ 5*36602ebaSeric.gao@rock-chips.com */ 6*36602ebaSeric.gao@rock-chips.com 7*36602ebaSeric.gao@rock-chips.com #ifndef __RK_MIPI_H 8*36602ebaSeric.gao@rock-chips.com #define __RK_MIPI_H 9*36602ebaSeric.gao@rock-chips.com 10*36602ebaSeric.gao@rock-chips.com struct rk_mipi_priv { 11*36602ebaSeric.gao@rock-chips.com ulong regs; 12*36602ebaSeric.gao@rock-chips.com void *grf; 13*36602ebaSeric.gao@rock-chips.com struct udevice *panel; 14*36602ebaSeric.gao@rock-chips.com struct mipi_dsi *dsi; 15*36602ebaSeric.gao@rock-chips.com u32 ref_clk; 16*36602ebaSeric.gao@rock-chips.com u32 sys_clk; 17*36602ebaSeric.gao@rock-chips.com u32 pix_clk; 18*36602ebaSeric.gao@rock-chips.com u32 phy_clk; 19*36602ebaSeric.gao@rock-chips.com u32 txbyte_clk; 20*36602ebaSeric.gao@rock-chips.com u32 txesc_clk; 21*36602ebaSeric.gao@rock-chips.com }; 22*36602ebaSeric.gao@rock-chips.com 23*36602ebaSeric.gao@rock-chips.com int rk_mipi_read_timing(struct udevice *dev, 24*36602ebaSeric.gao@rock-chips.com struct display_timing *timing); 25*36602ebaSeric.gao@rock-chips.com 26*36602ebaSeric.gao@rock-chips.com int rk_mipi_dsi_enable(struct udevice *dev, 27*36602ebaSeric.gao@rock-chips.com const struct display_timing *timing); 28*36602ebaSeric.gao@rock-chips.com 29*36602ebaSeric.gao@rock-chips.com int rk_mipi_phy_enable(struct udevice *dev); 30*36602ebaSeric.gao@rock-chips.com 31*36602ebaSeric.gao@rock-chips.com 32*36602ebaSeric.gao@rock-chips.com #endif 33