1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Eric Gao <eric.gao@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <display.h> 10 #include <dm.h> 11 #include <fdtdec.h> 12 #include <panel.h> 13 #include <regmap.h> 14 #include "rk_mipi.h" 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/hardware.h> 18 #include <asm/io.h> 19 #include <dm/uclass-internal.h> 20 #include <linux/kernel.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/cru_rk3399.h> 23 #include <asm/arch/grf_rk3399.h> 24 #include <asm/arch/rockchip_mipi_dsi.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int rk_mipi_read_timing(struct udevice *dev, 29 struct display_timing *timing) 30 { 31 int ret; 32 33 ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), 34 0, timing); 35 if (ret) { 36 debug("%s: Failed to decode display timing (ret=%d)\n", 37 __func__, ret); 38 return -EINVAL; 39 } 40 41 return 0; 42 } 43 44 /* 45 * Register write function used only for mipi dsi controller. 46 * Parameter: 47 * @regs: mipi controller address 48 * @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can 49 * use define in rk_mipi.h directly for this parameter 50 * @val: value that will be write to specified bits of register 51 */ 52 static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) 53 { 54 u32 dat; 55 u32 mask; 56 u32 offset = (reg >> OFFSET_SHIFT) & 0xff; 57 u32 bits = (reg >> BITS_SHIFT) & 0xff; 58 uintptr_t addr = (reg >> ADDR_SHIFT) + regs; 59 60 /* Mask for specifiled bits,the corresponding bits will be clear */ 61 mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); 62 63 /* Make sure val in the available range */ 64 val &= ~(0xffffffff << bits); 65 66 /* Get register's original val */ 67 dat = readl(addr); 68 69 /* Clear specified bits */ 70 dat &= mask; 71 72 /* Fill specified bits */ 73 dat |= val << offset; 74 75 writel(dat, addr); 76 } 77 78 int rk_mipi_dsi_enable(struct udevice *dev, 79 const struct display_timing *timing) 80 { 81 int node, timing_node; 82 int val; 83 struct rk_mipi_priv *priv = dev_get_priv(dev); 84 uintptr_t regs = priv->regs; 85 u32 txbyte_clk = priv->txbyte_clk; 86 u32 txesc_clk = priv->txesc_clk; 87 88 txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1); 89 90 /* Set Display timing parameter */ 91 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); 92 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); 93 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ 94 + timing->hback_porch.typ + timing->hactive.typ 95 + timing->hfront_porch.typ)); 96 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); 97 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); 98 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); 99 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); 100 101 /* Set Signal Polarity */ 102 val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0; 103 rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val); 104 105 val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0; 106 rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val); 107 108 val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0; 109 rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val); 110 111 val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0; 112 rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val); 113 114 /* Set video mode */ 115 rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE); 116 117 /* Set video mode transmission type as burst mode */ 118 rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE); 119 120 /* Set pix num in a video package */ 121 rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); 122 123 /* Set dpi color coding depth 24 bit */ 124 timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), 125 "display-timings"); 126 node = fdt_first_subnode(gd->fdt_blob, timing_node); 127 val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1); 128 switch (val) { 129 case 16: 130 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); 131 break; 132 case 24: 133 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); 134 break; 135 case 30: 136 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT); 137 break; 138 default: 139 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); 140 } 141 /* Enable low power mode */ 142 rk_mipi_dsi_write(regs, LP_CMD_EN, 1); 143 rk_mipi_dsi_write(regs, LP_HFP_EN, 1); 144 rk_mipi_dsi_write(regs, LP_VACT_EN, 1); 145 rk_mipi_dsi_write(regs, LP_VFP_EN, 1); 146 rk_mipi_dsi_write(regs, LP_VBP_EN, 1); 147 rk_mipi_dsi_write(regs, LP_VSA_EN, 1); 148 149 /* Division for timeout counter clk */ 150 rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a); 151 152 /* Tx esc clk division from txbyte clk */ 153 rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk); 154 155 /* Timeout count for hs<->lp transation between Line period */ 156 rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8); 157 158 /* Phy State transfer timing */ 159 rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32); 160 rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1); 161 rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14); 162 rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10); 163 rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710); 164 165 /* Power on */ 166 rk_mipi_dsi_write(regs, SHUTDOWNZ, 1); 167 168 return 0; 169 } 170 171 /* rk mipi dphy write function. It is used to write test data to dphy */ 172 static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code, 173 unsigned char *test_data, unsigned char size) 174 { 175 int i = 0; 176 177 /* Write Test code */ 178 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); 179 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code); 180 rk_mipi_dsi_write(regs, PHY_TESTEN, 1); 181 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); 182 rk_mipi_dsi_write(regs, PHY_TESTEN, 0); 183 184 /* Write Test data */ 185 for (i = 0; i < size; i++) { 186 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); 187 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]); 188 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); 189 } 190 } 191 192 /* 193 * Mipi dphy config function. Calculate the suitable prediv, feedback div, 194 * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate, 195 * and then enable phy. 196 */ 197 int rk_mipi_phy_enable(struct udevice *dev) 198 { 199 int i; 200 struct rk_mipi_priv *priv = dev_get_priv(dev); 201 uintptr_t regs = priv->regs; 202 u64 fbdiv; 203 u64 prediv = 1; 204 u32 max_fbdiv = 512; 205 u32 max_prediv, min_prediv; 206 u64 ddr_clk = priv->phy_clk; 207 u32 refclk = priv->ref_clk; 208 u32 remain = refclk; 209 unsigned char test_data[2] = {0}; 210 211 int freq_rang[][2] = { 212 {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01}, 213 {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12}, 214 {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23}, 215 {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15}, 216 {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07}, 217 {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09}, 218 {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a}, 219 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 220 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 221 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 222 }; 223 224 /* Shutdown mode */ 225 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0); 226 rk_mipi_dsi_write(regs, PHY_RSTZ, 0); 227 rk_mipi_dsi_write(regs, PHY_TESTCLR, 1); 228 229 /* Pll locking */ 230 rk_mipi_dsi_write(regs, PHY_TESTCLR, 0); 231 232 /* config cp and lfp */ 233 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; 234 rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1); 235 236 test_data[0] = 0x8; 237 rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1); 238 239 test_data[0] = 0x80 | 0x40; 240 rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1); 241 242 /* select the suitable value for fsfreqrang reg */ 243 for (i = 0; i < ARRAY_SIZE(freq_rang); i++) { 244 if (ddr_clk / (MHz) >= freq_rang[i][0]) 245 break; 246 } 247 if (i == ARRAY_SIZE(freq_rang)) { 248 debug("%s: Dphy freq out of range!\n", __func__); 249 return -EINVAL; 250 } 251 test_data[0] = freq_rang[i][1] << 1; 252 rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1); 253 254 /* 255 * Calculate the best ddrclk and it's corresponding div value. If the 256 * given pixelclock is great than 250M, ddrclk will be fix 1500M. 257 * Otherwise, 258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz 259 * according to spec. 260 */ 261 max_prediv = (refclk / (5 * MHz)); 262 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); 263 264 debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv, 265 min_prediv); 266 267 if (max_prediv < min_prediv) { 268 debug("%s: Invalid refclk value\n", __func__); 269 return -EINVAL; 270 } 271 272 /* Calculate the best refclk and feedback division value for dphy pll */ 273 for (i = min_prediv; i < max_prediv; i++) { 274 if ((ddr_clk * i % refclk < remain) && 275 (ddr_clk * i / refclk) < max_fbdiv) { 276 prediv = i; 277 remain = ddr_clk * i % refclk; 278 } 279 } 280 fbdiv = ddr_clk * prediv / refclk; 281 ddr_clk = refclk * fbdiv / prediv; 282 priv->phy_clk = ddr_clk; 283 284 debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n", 285 __func__, refclk, prediv, fbdiv, ddr_clk); 286 287 /* config prediv and feedback reg */ 288 test_data[0] = prediv - 1; 289 rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1); 290 test_data[0] = (fbdiv - 1) & 0x1f; 291 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); 292 test_data[0] = (fbdiv - 1) >> 5 | 0x80; 293 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); 294 test_data[0] = 0x30; 295 rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1); 296 297 /* rest config */ 298 test_data[0] = 0x4d; 299 rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1); 300 301 test_data[0] = 0x3d; 302 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); 303 304 test_data[0] = 0xdf; 305 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); 306 307 test_data[0] = 0x7; 308 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); 309 310 test_data[0] = 0x80 | 0x7; 311 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); 312 313 test_data[0] = 0x80 | 15; 314 rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME, 315 test_data, 1); 316 test_data[0] = 0x80 | 85; 317 rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME, 318 test_data, 1); 319 test_data[0] = 0x40 | 10; 320 rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME, 321 test_data, 1); 322 323 /* enter into stop mode */ 324 rk_mipi_dsi_write(regs, N_LANES, 0x03); 325 rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1); 326 rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1); 327 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1); 328 rk_mipi_dsi_write(regs, PHY_RSTZ, 1); 329 330 return 0; 331 } 332 333