1 /* 2 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd 3 * Author: Eric Gao <eric.gao@rock-chips.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <fdtdec.h> 13 #include <panel.h> 14 #include <regmap.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/hardware.h> 18 #include <asm/io.h> 19 #include <dm/uclass-internal.h> 20 #include <linux/kernel.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/cru_rk3399.h> 23 #include <asm/arch/grf_rk3399.h> 24 #include <asm/arch/rockchip_mipi_dsi.h> 25 #include <dt-bindings/clock/rk3288-cru.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * Private information for rk mipi 31 * 32 * @regs: mipi controller address 33 * @grf: GRF register 34 * @panel: panel assined by device tree 35 * @ref_clk: reference clock for mipi dsi pll 36 * @sysclk: config clock for mipi dsi register 37 * @pix_clk: pixel clock for vop->dsi data transmission 38 * @phy_clk: mipi dphy output clock 39 * @txbyte_clk: clock for dsi->dphy high speed data transmission 40 * @txesc_clk: clock for tx esc mode 41 */ 42 struct rk_mipi_priv { 43 uintptr_t regs; 44 struct rk3399_grf_regs *grf; 45 struct udevice *panel; 46 struct mipi_dsi *dsi; 47 u32 ref_clk; 48 u32 sys_clk; 49 u32 pix_clk; 50 u32 phy_clk; 51 u32 txbyte_clk; 52 u32 txesc_clk; 53 }; 54 55 static int rk_mipi_read_timing(struct udevice *dev, 56 struct display_timing *timing) 57 { 58 int ret; 59 60 ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), 61 0, timing); 62 if (ret) { 63 debug("%s: Failed to decode display timing (ret=%d)\n", 64 __func__, ret); 65 return -EINVAL; 66 } 67 68 return 0; 69 } 70 71 /* 72 * Register write function used only for mipi dsi controller. 73 * Parameter: 74 * @regs: mipi controller address 75 * @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can 76 * use define in rk_mipi.h directly for this parameter 77 * @val: value that will be write to specified bits of register 78 */ 79 static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) 80 { 81 u32 dat; 82 u32 mask; 83 u32 offset = (reg >> OFFSET_SHIFT) & 0xff; 84 u32 bits = (reg >> BITS_SHIFT) & 0xff; 85 uintptr_t addr = (reg >> ADDR_SHIFT) + regs; 86 87 /* Mask for specifiled bits,the corresponding bits will be clear */ 88 mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); 89 90 /* Make sure val in the available range */ 91 val &= ~(0xffffffff << bits); 92 93 /* Get register's original val */ 94 dat = readl(addr); 95 96 /* Clear specified bits */ 97 dat &= mask; 98 99 /* Fill specified bits */ 100 dat |= val << offset; 101 102 writel(dat, addr); 103 } 104 105 static int rk_mipi_dsi_enable(struct udevice *dev, 106 const struct display_timing *timing) 107 { 108 int node, timing_node; 109 int val; 110 struct rk_mipi_priv *priv = dev_get_priv(dev); 111 uintptr_t regs = priv->regs; 112 struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); 113 u32 txbyte_clk = priv->txbyte_clk; 114 u32 txesc_clk = priv->txesc_clk; 115 116 txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1); 117 118 /* Select the video source */ 119 switch (disp_uc_plat->source_id) { 120 case VOP_B: 121 rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, 122 GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT); 123 break; 124 case VOP_L: 125 rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, 126 GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT); 127 break; 128 default: 129 debug("%s: Invalid VOP id\n", __func__); 130 return -EINVAL; 131 } 132 133 /* Set Controller as TX mode */ 134 val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT; 135 rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); 136 137 /* Exit tx stop mode */ 138 val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT; 139 rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); 140 141 /* Disable turnequest */ 142 val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT; 143 rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); 144 145 /* Set Display timing parameter */ 146 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); 147 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); 148 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ 149 + timing->hback_porch.typ + timing->hactive.typ 150 + timing->hfront_porch.typ)); 151 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); 152 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); 153 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); 154 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); 155 156 /* Set Signal Polarity */ 157 val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0; 158 rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val); 159 160 val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0; 161 rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val); 162 163 val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0; 164 rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val); 165 166 val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0; 167 rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val); 168 169 /* Set video mode */ 170 rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE); 171 172 /* Set video mode transmission type as burst mode */ 173 rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE); 174 175 /* Set pix num in a video package */ 176 rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); 177 178 /* Set dpi color coding depth 24 bit */ 179 timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), 180 "display-timings"); 181 node = fdt_first_subnode(gd->fdt_blob, timing_node); 182 val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1); 183 switch (val) { 184 case 16: 185 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); 186 break; 187 case 24: 188 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); 189 break; 190 case 30: 191 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT); 192 break; 193 default: 194 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); 195 } 196 /* Enable low power mode */ 197 rk_mipi_dsi_write(regs, LP_CMD_EN, 1); 198 rk_mipi_dsi_write(regs, LP_HFP_EN, 1); 199 rk_mipi_dsi_write(regs, LP_VACT_EN, 1); 200 rk_mipi_dsi_write(regs, LP_VFP_EN, 1); 201 rk_mipi_dsi_write(regs, LP_VBP_EN, 1); 202 rk_mipi_dsi_write(regs, LP_VSA_EN, 1); 203 204 /* Division for timeout counter clk */ 205 rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a); 206 207 /* Tx esc clk division from txbyte clk */ 208 rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk); 209 210 /* Timeout count for hs<->lp transation between Line period */ 211 rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8); 212 213 /* Phy State transfer timing */ 214 rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32); 215 rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1); 216 rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14); 217 rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10); 218 rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710); 219 220 /* Power on */ 221 rk_mipi_dsi_write(regs, SHUTDOWNZ, 1); 222 223 return 0; 224 } 225 226 /* rk mipi dphy write function. It is used to write test data to dphy */ 227 static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code, 228 unsigned char *test_data, unsigned char size) 229 { 230 int i = 0; 231 232 /* Write Test code */ 233 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); 234 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code); 235 rk_mipi_dsi_write(regs, PHY_TESTEN, 1); 236 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); 237 rk_mipi_dsi_write(regs, PHY_TESTEN, 0); 238 239 /* Write Test data */ 240 for (i = 0; i < size; i++) { 241 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); 242 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]); 243 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); 244 } 245 } 246 247 /* 248 * Mipi dphy config function. Calculate the suitable prediv, feedback div, 249 * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate, 250 * and then enable phy. 251 */ 252 static int rk_mipi_phy_enable(struct udevice *dev) 253 { 254 int i; 255 struct rk_mipi_priv *priv = dev_get_priv(dev); 256 uintptr_t regs = priv->regs; 257 u64 fbdiv; 258 u64 prediv = 1; 259 u32 max_fbdiv = 512; 260 u32 max_prediv, min_prediv; 261 u64 ddr_clk = priv->phy_clk; 262 u32 refclk = priv->ref_clk; 263 u32 remain = refclk; 264 unsigned char test_data[2] = {0}; 265 266 int freq_rang[][2] = { 267 {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01}, 268 {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12}, 269 {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23}, 270 {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15}, 271 {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07}, 272 {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09}, 273 {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a}, 274 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b}, 275 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c}, 276 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} 277 }; 278 279 /* Shutdown mode */ 280 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0); 281 rk_mipi_dsi_write(regs, PHY_RSTZ, 0); 282 rk_mipi_dsi_write(regs, PHY_TESTCLR, 1); 283 284 /* Pll locking */ 285 rk_mipi_dsi_write(regs, PHY_TESTCLR, 0); 286 287 /* config cp and lfp */ 288 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; 289 rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1); 290 291 test_data[0] = 0x8; 292 rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1); 293 294 test_data[0] = 0x80 | 0x40; 295 rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1); 296 297 /* select the suitable value for fsfreqrang reg */ 298 for (i = 0; i < ARRAY_SIZE(freq_rang); i++) { 299 if (ddr_clk / (MHz) >= freq_rang[i][0]) 300 break; 301 } 302 if (i == ARRAY_SIZE(freq_rang)) { 303 debug("%s: Dphy freq out of range!\n", __func__); 304 return -EINVAL; 305 } 306 test_data[0] = freq_rang[i][1] << 1; 307 rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1); 308 309 /* 310 * Calculate the best ddrclk and it's corresponding div value. If the 311 * given pixelclock is great than 250M, ddrclk will be fix 1500M. 312 * Otherwise, 313 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz 314 * according to spec. 315 */ 316 max_prediv = (refclk / (5 * MHz)); 317 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); 318 319 debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv, 320 min_prediv); 321 322 if (max_prediv < min_prediv) { 323 debug("%s: Invalid refclk value\n", __func__); 324 return -EINVAL; 325 } 326 327 /* Calculate the best refclk and feedback division value for dphy pll */ 328 for (i = min_prediv; i < max_prediv; i++) { 329 if ((ddr_clk * i % refclk < remain) && 330 (ddr_clk * i / refclk) < max_fbdiv) { 331 prediv = i; 332 remain = ddr_clk * i % refclk; 333 } 334 } 335 fbdiv = ddr_clk * prediv / refclk; 336 ddr_clk = refclk * fbdiv / prediv; 337 priv->phy_clk = ddr_clk; 338 339 debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n", 340 __func__, refclk, prediv, fbdiv, ddr_clk); 341 342 /* config prediv and feedback reg */ 343 test_data[0] = prediv - 1; 344 rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1); 345 test_data[0] = (fbdiv - 1) & 0x1f; 346 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); 347 test_data[0] = (fbdiv - 1) >> 5 | 0x80; 348 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1); 349 test_data[0] = 0x30; 350 rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1); 351 352 /* rest config */ 353 test_data[0] = 0x4d; 354 rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1); 355 356 test_data[0] = 0x3d; 357 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); 358 359 test_data[0] = 0xdf; 360 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1); 361 362 test_data[0] = 0x7; 363 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); 364 365 test_data[0] = 0x80 | 0x7; 366 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1); 367 368 test_data[0] = 0x80 | 15; 369 rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME, 370 test_data, 1); 371 test_data[0] = 0x80 | 85; 372 rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME, 373 test_data, 1); 374 test_data[0] = 0x40 | 10; 375 rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME, 376 test_data, 1); 377 378 /* enter into stop mode */ 379 rk_mipi_dsi_write(regs, N_LANES, 0x03); 380 rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1); 381 rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1); 382 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1); 383 rk_mipi_dsi_write(regs, PHY_RSTZ, 1); 384 385 return 0; 386 } 387 388 /* 389 * This function is called by rk_display_init() using rk_mipi_dsi_enable() and 390 * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success, 391 * enable backlight. 392 */ 393 static int rk_display_enable(struct udevice *dev, int panel_bpp, 394 const struct display_timing *timing) 395 { 396 int ret; 397 struct rk_mipi_priv *priv = dev_get_priv(dev); 398 399 /* Fill the mipi controller parameter */ 400 priv->ref_clk = 24 * MHz; 401 priv->sys_clk = priv->ref_clk; 402 priv->pix_clk = timing->pixelclock.typ; 403 priv->phy_clk = priv->pix_clk * 6; 404 priv->txbyte_clk = priv->phy_clk / 8; 405 priv->txesc_clk = 20 * MHz; 406 407 /* Config and enable mipi dsi according to timing */ 408 ret = rk_mipi_dsi_enable(dev, timing); 409 if (ret) { 410 debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n", 411 __func__, ret); 412 return ret; 413 } 414 415 /* Config and enable mipi phy */ 416 ret = rk_mipi_phy_enable(dev); 417 if (ret) { 418 debug("%s: rk_mipi_phy_enable() failed (err=%d)\n", 419 __func__, ret); 420 return ret; 421 } 422 423 /* Enable backlight */ 424 ret = panel_enable_backlight(priv->panel); 425 if (ret) { 426 debug("%s: panel_enable_backlight() failed (err=%d)\n", 427 __func__, ret); 428 return ret; 429 } 430 431 return 0; 432 } 433 434 static int rk_mipi_ofdata_to_platdata(struct udevice *dev) 435 { 436 struct rk_mipi_priv *priv = dev_get_priv(dev); 437 438 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 439 if (priv->grf <= 0) { 440 debug("%s: Get syscon grf failed (ret=%p)\n", 441 __func__, priv->grf); 442 return -ENXIO; 443 } 444 priv->regs = devfdt_get_addr(dev); 445 if (priv->regs <= 0) { 446 debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__, 447 priv->regs); 448 return -ENXIO; 449 } 450 451 return 0; 452 } 453 454 /* 455 * Probe function: check panel existence and readingit's timing. Then config 456 * mipi dsi controller and enable it according to the timing parameter. 457 */ 458 static int rk_mipi_probe(struct udevice *dev) 459 { 460 int ret; 461 struct rk_mipi_priv *priv = dev_get_priv(dev); 462 463 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel", 464 &priv->panel); 465 if (ret) { 466 debug("%s: Can not find panel (err=%d)\n", __func__, ret); 467 return ret; 468 } 469 470 return 0; 471 } 472 473 static const struct dm_display_ops rk_mipi_dsi_ops = { 474 .read_timing = rk_mipi_read_timing, 475 .enable = rk_display_enable, 476 }; 477 478 static const struct udevice_id rk_mipi_dsi_ids[] = { 479 { .compatible = "rockchip,rk3399_mipi_dsi" }, 480 { } 481 }; 482 483 U_BOOT_DRIVER(rk_mipi_dsi) = { 484 .name = "rk_mipi_dsi", 485 .id = UCLASS_DISPLAY, 486 .of_match = rk_mipi_dsi_ids, 487 .ofdata_to_platdata = rk_mipi_ofdata_to_platdata, 488 .probe = rk_mipi_probe, 489 .ops = &rk_mipi_dsi_ops, 490 .priv_auto_alloc_size = sizeof(struct rk_mipi_priv), 491 }; 492