1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <dw_hdmi.h> 13 #include <edid.h> 14 #include <regmap.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/io.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/grf_rk3288.h> 20 #include <power/regulator.h> 21 22 struct rk_hdmi_priv { 23 struct dw_hdmi hdmi; 24 struct rk3288_grf *grf; 25 }; 26 27 static const struct hdmi_phy_config rockchip_phy_config[] = { 28 { 29 .mpixelclock = 74250000, 30 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, 31 }, { 32 .mpixelclock = 148500000, 33 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, 34 }, { 35 .mpixelclock = 297000000, 36 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, 37 }, { 38 .mpixelclock = ~0ul, 39 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000, 40 } 41 }; 42 43 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { 44 { 45 .mpixelclock = 40000000, 46 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, 47 }, { 48 .mpixelclock = 65000000, 49 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, 50 }, { 51 .mpixelclock = 66000000, 52 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, 53 }, { 54 .mpixelclock = 83500000, 55 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, 56 }, { 57 .mpixelclock = 146250000, 58 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, 59 }, { 60 .mpixelclock = 148500000, 61 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, 62 }, { 63 .mpixelclock = ~0ul, 64 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, 65 } 66 }; 67 68 static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) 69 { 70 struct rk_hdmi_priv *priv = dev_get_priv(dev); 71 72 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); 73 } 74 75 static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, 76 const struct display_timing *edid) 77 { 78 struct rk_hdmi_priv *priv = dev_get_priv(dev); 79 80 return dw_hdmi_enable(&priv->hdmi, edid); 81 } 82 83 static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) 84 { 85 struct rk_hdmi_priv *priv = dev_get_priv(dev); 86 struct dw_hdmi *hdmi = &priv->hdmi; 87 88 hdmi->ioaddr = (ulong)devfdt_get_addr(dev); 89 hdmi->mpll_cfg = rockchip_mpll_cfg; 90 hdmi->phy_cfg = rockchip_phy_config; 91 hdmi->i2c_clk_high = 0x7a; 92 hdmi->i2c_clk_low = 0x8d; 93 94 /* 95 * TODO(sjg@chromium.org): The above values don't work - these ones 96 * work better, but generate lots of errors in the data. 97 */ 98 hdmi->i2c_clk_high = 0x0d; 99 hdmi->i2c_clk_low = 0x0d; 100 hdmi->reg_io_width = 4; 101 hdmi->phy_set = dw_hdmi_phy_cfg; 102 103 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 104 105 return 0; 106 } 107 108 static int rk_hdmi_probe(struct udevice *dev) 109 { 110 struct display_plat *uc_plat = dev_get_uclass_platdata(dev); 111 struct rk_hdmi_priv *priv = dev_get_priv(dev); 112 struct dw_hdmi *hdmi = &priv->hdmi; 113 struct udevice *reg; 114 struct clk clk; 115 int ret; 116 int vop_id = uc_plat->source_id; 117 118 ret = clk_get_by_index(dev, 0, &clk); 119 if (ret >= 0) { 120 ret = clk_set_rate(&clk, 0); 121 clk_free(&clk); 122 } 123 if (ret) { 124 debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret); 125 return ret; 126 } 127 128 /* 129 * Configure the maximum clock to permit whatever resolution the 130 * monitor wants 131 */ 132 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); 133 if (ret >= 0) { 134 ret = clk_set_rate(&clk, 384000000); 135 clk_free(&clk); 136 } 137 if (ret < 0) { 138 debug("%s: Failed to set clock in source device '%s': ret=%d\n", 139 __func__, uc_plat->src_dev->name, ret); 140 return ret; 141 } 142 143 ret = regulator_get_by_platname("vcc50_hdmi", ®); 144 if (!ret) 145 ret = regulator_set_enable(reg, true); 146 if (ret) 147 debug("%s: Cannot set regulator vcc50_hdmi\n", __func__); 148 149 /* hdmi source select hdmi controller */ 150 rk_setreg(&priv->grf->soc_con6, 1 << 15); 151 152 /* hdmi data from vop id */ 153 rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, 154 (vop_id == 1) ? (1 << 4) : 0); 155 156 ret = dw_hdmi_phy_wait_for_hpd(hdmi); 157 if (ret < 0) { 158 debug("hdmi can not get hpd signal\n"); 159 return -1; 160 } 161 162 dw_hdmi_init(hdmi); 163 dw_hdmi_phy_init(hdmi); 164 165 return 0; 166 } 167 168 static const struct dm_display_ops rk_hdmi_ops = { 169 .read_edid = rk_hdmi_read_edid, 170 .enable = rk_hdmi_enable, 171 }; 172 173 static const struct udevice_id rk_hdmi_ids[] = { 174 { .compatible = "rockchip,rk3288-dw-hdmi" }, 175 { } 176 }; 177 178 U_BOOT_DRIVER(hdmi_rockchip) = { 179 .name = "hdmi_rockchip", 180 .id = UCLASS_DISPLAY, 181 .of_match = rk_hdmi_ids, 182 .ops = &rk_hdmi_ops, 183 .ofdata_to_platdata = rk_hdmi_ofdata_to_platdata, 184 .probe = rk_hdmi_probe, 185 .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv), 186 }; 187