1 /*
2  * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
3  * Author: Eric Gao <eric.gao@rock-chips.com>
4  *
5  * SPDX-License-Identifier: GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <clk.h>
10 #include <display.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <panel.h>
14 #include <regmap.h>
15 #include "rk_mipi.h"
16 #include <syscon.h>
17 #include <asm/gpio.h>
18 #include <asm/hardware.h>
19 #include <asm/io.h>
20 #include <dm/uclass-internal.h>
21 #include <linux/kernel.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/cru_rk3288.h>
24 #include <asm/arch/grf_rk3288.h>
25 #include <asm/arch/rockchip_mipi_dsi.h>
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 #define MHz 1000000
30 
31 /* Select mipi dsi source, big or little vop */
32 static int rk_mipi_dsi_source_select(struct udevice *dev)
33 {
34 	struct rk_mipi_priv *priv = dev_get_priv(dev);
35 	struct rk3288_grf *grf = priv->grf;
36 	struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
37 
38 	/* Select the video source */
39 	switch (disp_uc_plat->source_id) {
40 	case VOP_B:
41 		rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
42 			     RK3288_DSI0_LCDC_SEL_BIG
43 			     << RK3288_DSI0_LCDC_SEL_SHIFT);
44 		break;
45 	case VOP_L:
46 		rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
47 			     RK3288_DSI0_LCDC_SEL_LIT
48 			     << RK3288_DSI0_LCDC_SEL_SHIFT);
49 		break;
50 	default:
51 		debug("%s: Invalid VOP id\n", __func__);
52 		return -EINVAL;
53 	}
54 
55 	return 0;
56 }
57 
58 /* Setup mipi dphy working mode */
59 static void rk_mipi_dphy_mode_set(struct udevice *dev)
60 {
61 	struct rk_mipi_priv *priv = dev_get_priv(dev);
62 	struct rk3288_grf *grf = priv->grf;
63 	int val;
64 
65 	/* Set Controller as TX mode */
66 	val = RK3288_DPHY_TX0_RXMODE_DIS << RK3288_DPHY_TX0_RXMODE_SHIFT;
67 	rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val);
68 
69 	/* Exit tx stop mode */
70 	val |= RK3288_DPHY_TX0_TXSTOPMODE_EN
71 			<< RK3288_DPHY_TX0_TXSTOPMODE_SHIFT;
72 	rk_clrsetreg(&grf->soc_con8,
73 		     RK3288_DPHY_TX0_TXSTOPMODE_MASK, val);
74 
75 	/* Disable turnequest */
76 	val |= RK3288_DPHY_TX0_TURNREQUEST_EN
77 		<< RK3288_DPHY_TX0_TURNREQUEST_SHIFT;
78 	rk_clrsetreg(&grf->soc_con8,
79 		     RK3288_DPHY_TX0_TURNREQUEST_MASK, val);
80 }
81 
82 /*
83  * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
84  * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
85  * enable backlight.
86  */
87 static int rk_mipi_enable(struct udevice *dev, int panel_bpp,
88 			  const struct display_timing *timing)
89 {
90 	int ret;
91 	struct rk_mipi_priv *priv = dev_get_priv(dev);
92 
93 	/* Fill the mipi controller parameter */
94 	priv->ref_clk = 24 * MHz;
95 	priv->sys_clk = priv->ref_clk;
96 	priv->pix_clk = timing->pixelclock.typ;
97 	priv->phy_clk = priv->pix_clk * 6;
98 	priv->txbyte_clk = priv->phy_clk / 8;
99 	priv->txesc_clk = 20 * MHz;
100 
101 	/* Select vop port, big or little */
102 	rk_mipi_dsi_source_select(dev);
103 
104 	/* Set mipi dphy work mode */
105 	rk_mipi_dphy_mode_set(dev);
106 
107 	/* Config  and enable mipi dsi according to timing */
108 	ret = rk_mipi_dsi_enable(dev, timing);
109 	if (ret) {
110 		debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
111 		      __func__, ret);
112 		return ret;
113 	}
114 
115 	/* Config and enable mipi phy */
116 	ret = rk_mipi_phy_enable(dev);
117 	if (ret) {
118 		debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
119 		      __func__, ret);
120 		return ret;
121 	}
122 
123 	/* Enable backlight */
124 	ret = panel_enable_backlight(priv->panel);
125 	if (ret) {
126 		debug("%s: panel_enable_backlight() failed (err=%d)\n",
127 		      __func__, ret);
128 		return ret;
129 	}
130 
131 	return 0;
132 }
133 
134 static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
135 {
136 	struct rk_mipi_priv *priv = dev_get_priv(dev);
137 
138 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
139 	if (IS_ERR_OR_NULL(priv->grf)) {
140 		debug("%s: Get syscon grf failed (ret=%p)\n",
141 		      __func__, priv->grf);
142 		return  -ENXIO;
143 	}
144 	priv->regs = dev_read_addr(dev);
145 	if (priv->regs == FDT_ADDR_T_NONE) {
146 		debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__,
147 		      priv->regs);
148 		return  -ENXIO;
149 	}
150 
151 	return 0;
152 }
153 
154 /*
155  * Probe function: check panel existence and readingit's timing. Then config
156  * mipi dsi controller and enable it according to the timing parameter.
157  */
158 static int rk_mipi_probe(struct udevice *dev)
159 {
160 	int ret;
161 	struct rk_mipi_priv *priv = dev_get_priv(dev);
162 
163 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
164 					   &priv->panel);
165 	if (ret) {
166 		debug("%s: Can not find panel (err=%d)\n", __func__, ret);
167 		return ret;
168 	}
169 
170 	return 0;
171 }
172 
173 static const struct dm_display_ops rk_mipi_dsi_ops = {
174 	.read_timing = rk_mipi_read_timing,
175 	.enable = rk_mipi_enable,
176 };
177 
178 static const struct udevice_id rk_mipi_dsi_ids[] = {
179 	{ .compatible = "rockchip,rk3288_mipi_dsi" },
180 	{ }
181 };
182 
183 U_BOOT_DRIVER(rk_mipi_dsi) = {
184 	.name	= "rk_mipi_dsi",
185 	.id	= UCLASS_DISPLAY,
186 	.of_match = rk_mipi_dsi_ids,
187 	.ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
188 	.probe	= rk_mipi_probe,
189 	.ops	= &rk_mipi_dsi_ops,
190 	.priv_auto_alloc_size   = sizeof(struct rk_mipi_priv),
191 };
192