1fb8ddc24SMarek Vasut /* 2fb8ddc24SMarek Vasut * Freescale i.MX23/i.MX28 LCDIF driver 3fb8ddc24SMarek Vasut * 4fb8ddc24SMarek Vasut * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de> 5fb8ddc24SMarek Vasut * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7fb8ddc24SMarek Vasut */ 8fb8ddc24SMarek Vasut #include <common.h> 9fb8ddc24SMarek Vasut #include <malloc.h> 10fb8ddc24SMarek Vasut #include <video_fb.h> 11fb8ddc24SMarek Vasut 12fb8ddc24SMarek Vasut #include <asm/arch/imx-regs.h> 13fb8ddc24SMarek Vasut #include <asm/arch/clock.h> 14fb8ddc24SMarek Vasut #include <asm/arch/sys_proto.h> 15fb8ddc24SMarek Vasut #include <asm/errno.h> 16fb8ddc24SMarek Vasut #include <asm/io.h> 17fb8ddc24SMarek Vasut 1884f957f8SMarek Vasut #include <asm/imx-common/dma.h> 1984f957f8SMarek Vasut 20fb8ddc24SMarek Vasut #include "videomodes.h" 21fb8ddc24SMarek Vasut 22fb8ddc24SMarek Vasut #define PS2KHZ(ps) (1000000000UL / (ps)) 23fb8ddc24SMarek Vasut 24fb8ddc24SMarek Vasut static GraphicDevice panel; 2584f957f8SMarek Vasut struct mxs_dma_desc desc; 26fb8ddc24SMarek Vasut 279de4b729SMarek Vasut /** 289de4b729SMarek Vasut * mxsfb_system_setup() - Fine-tune LCDIF configuration 299de4b729SMarek Vasut * 309de4b729SMarek Vasut * This function is used to adjust the LCDIF configuration. This is usually 319de4b729SMarek Vasut * needed when driving the controller in System-Mode to operate an 8080 or 329de4b729SMarek Vasut * 6800 connected SmartLCD. 339de4b729SMarek Vasut */ 349de4b729SMarek Vasut __weak void mxsfb_system_setup(void) 359de4b729SMarek Vasut { 369de4b729SMarek Vasut } 379de4b729SMarek Vasut 38fb8ddc24SMarek Vasut /* 39fb8ddc24SMarek Vasut * DENX M28EVK: 40fb8ddc24SMarek Vasut * setenv videomode 41fb8ddc24SMarek Vasut * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066, 42fb8ddc24SMarek Vasut * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0 4311f98d1fSFabio Estevam * 4411f98d1fSFabio Estevam * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel: 4511f98d1fSFabio Estevam * setenv videomode 4611f98d1fSFabio Estevam * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851, 4711f98d1fSFabio Estevam * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 48fb8ddc24SMarek Vasut */ 49fb8ddc24SMarek Vasut 50fb8ddc24SMarek Vasut static void mxs_lcd_init(GraphicDevice *panel, 51fb8ddc24SMarek Vasut struct ctfb_res_modes *mode, int bpp) 52fb8ddc24SMarek Vasut { 53fb8ddc24SMarek Vasut struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; 54fb8ddc24SMarek Vasut uint32_t word_len = 0, bus_width = 0; 55fb8ddc24SMarek Vasut uint8_t valid_data = 0; 56fb8ddc24SMarek Vasut 57fb8ddc24SMarek Vasut /* Kick in the LCDIF clock */ 5895ae7000SPeng Fan mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); 59fb8ddc24SMarek Vasut 60fb8ddc24SMarek Vasut /* Restart the LCDIF block */ 61fb8ddc24SMarek Vasut mxs_reset_block(®s->hw_lcdif_ctrl_reg); 62fb8ddc24SMarek Vasut 63fb8ddc24SMarek Vasut switch (bpp) { 64fb8ddc24SMarek Vasut case 24: 65fb8ddc24SMarek Vasut word_len = LCDIF_CTRL_WORD_LENGTH_24BIT; 66fb8ddc24SMarek Vasut bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT; 67fb8ddc24SMarek Vasut valid_data = 0x7; 68fb8ddc24SMarek Vasut break; 69fb8ddc24SMarek Vasut case 18: 70fb8ddc24SMarek Vasut word_len = LCDIF_CTRL_WORD_LENGTH_24BIT; 71fb8ddc24SMarek Vasut bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT; 72fb8ddc24SMarek Vasut valid_data = 0x7; 73fb8ddc24SMarek Vasut break; 74fb8ddc24SMarek Vasut case 16: 75fb8ddc24SMarek Vasut word_len = LCDIF_CTRL_WORD_LENGTH_16BIT; 76fb8ddc24SMarek Vasut bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT; 77fb8ddc24SMarek Vasut valid_data = 0xf; 78fb8ddc24SMarek Vasut break; 79fb8ddc24SMarek Vasut case 8: 80fb8ddc24SMarek Vasut word_len = LCDIF_CTRL_WORD_LENGTH_8BIT; 81fb8ddc24SMarek Vasut bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT; 82fb8ddc24SMarek Vasut valid_data = 0xf; 83fb8ddc24SMarek Vasut break; 84fb8ddc24SMarek Vasut } 85fb8ddc24SMarek Vasut 86fb8ddc24SMarek Vasut writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE | 87fb8ddc24SMarek Vasut LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER, 88fb8ddc24SMarek Vasut ®s->hw_lcdif_ctrl); 89fb8ddc24SMarek Vasut 90fb8ddc24SMarek Vasut writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET, 91fb8ddc24SMarek Vasut ®s->hw_lcdif_ctrl1); 929de4b729SMarek Vasut 939de4b729SMarek Vasut mxsfb_system_setup(); 949de4b729SMarek Vasut 95fb8ddc24SMarek Vasut writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres, 96fb8ddc24SMarek Vasut ®s->hw_lcdif_transfer_count); 97fb8ddc24SMarek Vasut 98fb8ddc24SMarek Vasut writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL | 99fb8ddc24SMarek Vasut LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | 100fb8ddc24SMarek Vasut LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | 101fb8ddc24SMarek Vasut mode->vsync_len, ®s->hw_lcdif_vdctrl0); 102fb8ddc24SMarek Vasut writel(mode->upper_margin + mode->lower_margin + 103fb8ddc24SMarek Vasut mode->vsync_len + mode->yres, 104fb8ddc24SMarek Vasut ®s->hw_lcdif_vdctrl1); 105fb8ddc24SMarek Vasut writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) | 106fb8ddc24SMarek Vasut (mode->left_margin + mode->right_margin + 107fb8ddc24SMarek Vasut mode->hsync_len + mode->xres), 108fb8ddc24SMarek Vasut ®s->hw_lcdif_vdctrl2); 109fb8ddc24SMarek Vasut writel(((mode->left_margin + mode->hsync_len) << 110fb8ddc24SMarek Vasut LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) | 111fb8ddc24SMarek Vasut (mode->upper_margin + mode->vsync_len), 112fb8ddc24SMarek Vasut ®s->hw_lcdif_vdctrl3); 113fb8ddc24SMarek Vasut writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres, 114fb8ddc24SMarek Vasut ®s->hw_lcdif_vdctrl4); 115fb8ddc24SMarek Vasut 116fb8ddc24SMarek Vasut writel(panel->frameAdrs, ®s->hw_lcdif_cur_buf); 117fb8ddc24SMarek Vasut writel(panel->frameAdrs, ®s->hw_lcdif_next_buf); 118fb8ddc24SMarek Vasut 119fb8ddc24SMarek Vasut /* Flush FIFO first */ 120fb8ddc24SMarek Vasut writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set); 121fb8ddc24SMarek Vasut 1229de4b729SMarek Vasut #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM 123fb8ddc24SMarek Vasut /* Sync signals ON */ 124fb8ddc24SMarek Vasut setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON); 1259de4b729SMarek Vasut #endif 126fb8ddc24SMarek Vasut 127fb8ddc24SMarek Vasut /* FIFO cleared */ 128fb8ddc24SMarek Vasut writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr); 129fb8ddc24SMarek Vasut 130fb8ddc24SMarek Vasut /* RUN! */ 131fb8ddc24SMarek Vasut writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); 132fb8ddc24SMarek Vasut } 133fb8ddc24SMarek Vasut 134*a3c252d6SPeng Fan void lcdif_power_down(void) 135*a3c252d6SPeng Fan { 136*a3c252d6SPeng Fan struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; 137*a3c252d6SPeng Fan int timeout = 1000000; 138*a3c252d6SPeng Fan 139*a3c252d6SPeng Fan writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg); 140*a3c252d6SPeng Fan writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg); 141*a3c252d6SPeng Fan writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr); 142*a3c252d6SPeng Fan while (--timeout) { 143*a3c252d6SPeng Fan if (readl(®s->hw_lcdif_ctrl1_reg) & 144*a3c252d6SPeng Fan LCDIF_CTRL1_VSYNC_EDGE_IRQ) 145*a3c252d6SPeng Fan break; 146*a3c252d6SPeng Fan udelay(1); 147*a3c252d6SPeng Fan } 148*a3c252d6SPeng Fan mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg); 149*a3c252d6SPeng Fan } 150*a3c252d6SPeng Fan 151fb8ddc24SMarek Vasut void *video_hw_init(void) 152fb8ddc24SMarek Vasut { 153fb8ddc24SMarek Vasut int bpp = -1; 154fb8ddc24SMarek Vasut char *penv; 155fb8ddc24SMarek Vasut void *fb; 156fb8ddc24SMarek Vasut struct ctfb_res_modes mode; 157fb8ddc24SMarek Vasut 158fb8ddc24SMarek Vasut puts("Video: "); 159fb8ddc24SMarek Vasut 160fb8ddc24SMarek Vasut /* Suck display configuration from "videomode" variable */ 161fb8ddc24SMarek Vasut penv = getenv("videomode"); 162fb8ddc24SMarek Vasut if (!penv) { 163620ca1c1SFabio Estevam puts("MXSFB: 'videomode' variable not set!\n"); 164fb8ddc24SMarek Vasut return NULL; 165fb8ddc24SMarek Vasut } 166fb8ddc24SMarek Vasut 167fb8ddc24SMarek Vasut bpp = video_get_params(&mode, penv); 168fb8ddc24SMarek Vasut 169fb8ddc24SMarek Vasut /* fill in Graphic device struct */ 170fb8ddc24SMarek Vasut sprintf(panel.modeIdent, "%dx%dx%d", 171fb8ddc24SMarek Vasut mode.xres, mode.yres, bpp); 172fb8ddc24SMarek Vasut 173fb8ddc24SMarek Vasut panel.winSizeX = mode.xres; 174fb8ddc24SMarek Vasut panel.winSizeY = mode.yres; 175fb8ddc24SMarek Vasut panel.plnSizeX = mode.xres; 176fb8ddc24SMarek Vasut panel.plnSizeY = mode.yres; 177fb8ddc24SMarek Vasut 178fb8ddc24SMarek Vasut switch (bpp) { 179fb8ddc24SMarek Vasut case 24: 180fb8ddc24SMarek Vasut case 18: 181fb8ddc24SMarek Vasut panel.gdfBytesPP = 4; 182fb8ddc24SMarek Vasut panel.gdfIndex = GDF_32BIT_X888RGB; 183fb8ddc24SMarek Vasut break; 184fb8ddc24SMarek Vasut case 16: 185fb8ddc24SMarek Vasut panel.gdfBytesPP = 2; 186fb8ddc24SMarek Vasut panel.gdfIndex = GDF_16BIT_565RGB; 187fb8ddc24SMarek Vasut break; 188fb8ddc24SMarek Vasut case 8: 189fb8ddc24SMarek Vasut panel.gdfBytesPP = 1; 190fb8ddc24SMarek Vasut panel.gdfIndex = GDF__8BIT_INDEX; 191fb8ddc24SMarek Vasut break; 192fb8ddc24SMarek Vasut default: 193fb8ddc24SMarek Vasut printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp); 194fb8ddc24SMarek Vasut return NULL; 195fb8ddc24SMarek Vasut } 196fb8ddc24SMarek Vasut 197fb8ddc24SMarek Vasut panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; 198fb8ddc24SMarek Vasut 199fb8ddc24SMarek Vasut /* Allocate framebuffer */ 200e57baf5dSMarek Vasut fb = memalign(ARCH_DMA_MINALIGN, 201e57baf5dSMarek Vasut roundup(panel.memSize, ARCH_DMA_MINALIGN)); 202fb8ddc24SMarek Vasut if (!fb) { 203fb8ddc24SMarek Vasut printf("MXSFB: Error allocating framebuffer!\n"); 204fb8ddc24SMarek Vasut return NULL; 205fb8ddc24SMarek Vasut } 206fb8ddc24SMarek Vasut 207fb8ddc24SMarek Vasut /* Wipe framebuffer */ 208fb8ddc24SMarek Vasut memset(fb, 0, panel.memSize); 209fb8ddc24SMarek Vasut 210fb8ddc24SMarek Vasut panel.frameAdrs = (u32)fb; 211fb8ddc24SMarek Vasut 212fb8ddc24SMarek Vasut printf("%s\n", panel.modeIdent); 213fb8ddc24SMarek Vasut 214fb8ddc24SMarek Vasut /* Start framebuffer */ 215fb8ddc24SMarek Vasut mxs_lcd_init(&panel, &mode, bpp); 216fb8ddc24SMarek Vasut 21784f957f8SMarek Vasut #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM 21884f957f8SMarek Vasut /* 21984f957f8SMarek Vasut * If the LCD runs in system mode, the LCD refresh has to be triggered 22084f957f8SMarek Vasut * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid 22184f957f8SMarek Vasut * having to set this bit manually after every single change in the 22284f957f8SMarek Vasut * framebuffer memory, we set up specially crafted circular DMA, which 22384f957f8SMarek Vasut * sets the RUN bit, then waits until it gets cleared and repeats this 22484f957f8SMarek Vasut * infinitelly. This way, we get smooth continuous updates of the LCD. 22584f957f8SMarek Vasut */ 22684f957f8SMarek Vasut struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; 22784f957f8SMarek Vasut 22884f957f8SMarek Vasut memset(&desc, 0, sizeof(struct mxs_dma_desc)); 22984f957f8SMarek Vasut desc.address = (dma_addr_t)&desc; 23084f957f8SMarek Vasut desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 23184f957f8SMarek Vasut MXS_DMA_DESC_WAIT4END | 23284f957f8SMarek Vasut (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 23384f957f8SMarek Vasut desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN; 23484f957f8SMarek Vasut desc.cmd.next = (uint32_t)&desc.cmd; 23584f957f8SMarek Vasut 23684f957f8SMarek Vasut /* Execute the DMA chain. */ 23784f957f8SMarek Vasut mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); 23884f957f8SMarek Vasut #endif 23984f957f8SMarek Vasut 240fb8ddc24SMarek Vasut return (void *)&panel; 241fb8ddc24SMarek Vasut } 242