1 /* 2 * Copyright (C) 2009 3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 4 * Copyright (C) 2011 5 * HALE electronic GmbH, <helmut.raiger@hale.at> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <malloc.h> 11 #include <video_fb.h> 12 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 15 #include <linux/errno.h> 16 #include <asm/io.h> 17 18 #include "videomodes.h" 19 20 /* this might need panel specific set-up as-well */ 21 #define IF_CONF 0 22 23 /* -------------- controller specific stuff -------------- */ 24 25 /* IPU DMA Controller channel definitions. */ 26 enum ipu_channel { 27 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ 28 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ 29 IDMAC_ADC_0 = 1, 30 IDMAC_IC_2 = 2, 31 IDMAC_ADC_1 = 2, 32 IDMAC_IC_3 = 3, 33 IDMAC_IC_4 = 4, 34 IDMAC_IC_5 = 5, 35 IDMAC_IC_6 = 6, 36 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ 37 IDMAC_IC_8 = 8, 38 IDMAC_IC_9 = 9, 39 IDMAC_IC_10 = 10, 40 IDMAC_IC_11 = 11, 41 IDMAC_IC_12 = 12, 42 IDMAC_IC_13 = 13, 43 IDMAC_SDC_0 = 14, /* Background synchronous display data */ 44 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ 45 IDMAC_SDC_2 = 16, 46 IDMAC_SDC_3 = 17, 47 IDMAC_ADC_2 = 18, 48 IDMAC_ADC_3 = 19, 49 IDMAC_ADC_4 = 20, 50 IDMAC_ADC_5 = 21, 51 IDMAC_ADC_6 = 22, 52 IDMAC_ADC_7 = 23, 53 IDMAC_PF_0 = 24, 54 IDMAC_PF_1 = 25, 55 IDMAC_PF_2 = 26, 56 IDMAC_PF_3 = 27, 57 IDMAC_PF_4 = 28, 58 IDMAC_PF_5 = 29, 59 IDMAC_PF_6 = 30, 60 IDMAC_PF_7 = 31, 61 }; 62 63 /* More formats can be copied from the Linux driver if needed */ 64 enum pixel_fmt { 65 /* 2 bytes */ 66 IPU_PIX_FMT_RGB565, 67 IPU_PIX_FMT_RGB666, 68 IPU_PIX_FMT_BGR666, 69 /* 3 bytes */ 70 IPU_PIX_FMT_RGB24, 71 }; 72 73 struct pixel_fmt_cfg { 74 u32 b0; 75 u32 b1; 76 u32 b2; 77 u32 acc; 78 }; 79 80 static struct pixel_fmt_cfg fmt_cfg[] = { 81 [IPU_PIX_FMT_RGB24] = { 82 0x1600AAAA, 0x00E05555, 0x00070000, 3, 83 }, 84 [IPU_PIX_FMT_RGB666] = { 85 0x0005000F, 0x000B000F, 0x0011000F, 1, 86 }, 87 [IPU_PIX_FMT_BGR666] = { 88 0x0011000F, 0x000B000F, 0x0005000F, 1, 89 }, 90 [IPU_PIX_FMT_RGB565] = { 91 0x0004003F, 0x000A000F, 0x000F003F, 1, 92 } 93 }; 94 95 enum ipu_panel { 96 IPU_PANEL_SHARP_TFT, 97 IPU_PANEL_TFT, 98 }; 99 100 /* IPU Common registers */ 101 /* IPU_CONF and its bits already defined in imx-regs.h */ 102 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) 103 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) 104 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) 105 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) 106 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) 107 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) 108 #define IPU_TASKS_STAT (0x1C + IPU_BASE) 109 #define IPU_IMA_ADDR (0x20 + IPU_BASE) 110 #define IPU_IMA_DATA (0x24 + IPU_BASE) 111 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE) 112 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE) 113 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE) 114 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE) 115 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE) 116 #define IPU_INT_STAT_1 (0x3C + IPU_BASE) 117 #define IPU_INT_STAT_2 (0x40 + IPU_BASE) 118 #define IPU_INT_STAT_3 (0x44 + IPU_BASE) 119 #define IPU_INT_STAT_4 (0x48 + IPU_BASE) 120 #define IPU_INT_STAT_5 (0x4C + IPU_BASE) 121 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) 122 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) 123 #define IPU_BRK_STAT (0x58 + IPU_BASE) 124 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE) 125 126 /* Image Converter Registers */ 127 #define IC_CONF (0x88 + IPU_BASE) 128 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE) 129 #define IC_PRP_VF_RSC (0x90 + IPU_BASE) 130 #define IC_PP_RSC (0x94 + IPU_BASE) 131 #define IC_CMBP_1 (0x98 + IPU_BASE) 132 #define IC_CMBP_2 (0x9C + IPU_BASE) 133 #define PF_CONF (0xA0 + IPU_BASE) 134 #define IDMAC_CONF (0xA4 + IPU_BASE) 135 #define IDMAC_CHA_EN (0xA8 + IPU_BASE) 136 #define IDMAC_CHA_PRI (0xAC + IPU_BASE) 137 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) 138 139 /* Image Converter Register bits */ 140 #define IC_CONF_PRPENC_EN 0x00000001 141 #define IC_CONF_PRPENC_CSC1 0x00000002 142 #define IC_CONF_PRPENC_ROT_EN 0x00000004 143 #define IC_CONF_PRPVF_EN 0x00000100 144 #define IC_CONF_PRPVF_CSC1 0x00000200 145 #define IC_CONF_PRPVF_CSC2 0x00000400 146 #define IC_CONF_PRPVF_CMB 0x00000800 147 #define IC_CONF_PRPVF_ROT_EN 0x00001000 148 #define IC_CONF_PP_EN 0x00010000 149 #define IC_CONF_PP_CSC1 0x00020000 150 #define IC_CONF_PP_CSC2 0x00040000 151 #define IC_CONF_PP_CMB 0x00080000 152 #define IC_CONF_PP_ROT_EN 0x00100000 153 #define IC_CONF_IC_GLB_LOC_A 0x10000000 154 #define IC_CONF_KEY_COLOR_EN 0x20000000 155 #define IC_CONF_RWS_EN 0x40000000 156 #define IC_CONF_CSI_MEM_WR_EN 0x80000000 157 158 /* SDC Registers */ 159 #define SDC_COM_CONF (0xB4 + IPU_BASE) 160 #define SDC_GW_CTRL (0xB8 + IPU_BASE) 161 #define SDC_FG_POS (0xBC + IPU_BASE) 162 #define SDC_BG_POS (0xC0 + IPU_BASE) 163 #define SDC_CUR_POS (0xC4 + IPU_BASE) 164 #define SDC_PWM_CTRL (0xC8 + IPU_BASE) 165 #define SDC_CUR_MAP (0xCC + IPU_BASE) 166 #define SDC_HOR_CONF (0xD0 + IPU_BASE) 167 #define SDC_VER_CONF (0xD4 + IPU_BASE) 168 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) 169 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) 170 171 /* Register bits */ 172 #define SDC_COM_TFT_COLOR 0x00000001UL 173 #define SDC_COM_FG_EN 0x00000010UL 174 #define SDC_COM_GWSEL 0x00000020UL 175 #define SDC_COM_GLB_A 0x00000040UL 176 #define SDC_COM_KEY_COLOR_G 0x00000080UL 177 #define SDC_COM_BG_EN 0x00000200UL 178 #define SDC_COM_SHARP 0x00001000UL 179 180 #define SDC_V_SYNC_WIDTH_L 0x00000001UL 181 182 /* Display Interface registers */ 183 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE) 184 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE) 185 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE) 186 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) 187 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE) 188 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) 189 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) 190 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) 191 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) 192 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) 193 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) 194 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) 195 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) 196 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) 197 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) 198 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) 199 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) 200 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) 201 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) 202 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) 203 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) 204 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) 205 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) 206 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) 207 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) 208 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) 209 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) 210 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) 211 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) 212 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) 213 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) 214 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) 215 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) 216 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) 217 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) 218 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) 219 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) 220 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) 221 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) 222 223 /* DI_DISP_SIG_POL bits */ 224 #define DI_D3_VSYNC_POL (1 << 28) 225 #define DI_D3_HSYNC_POL (1 << 27) 226 #define DI_D3_DRDY_SHARP_POL (1 << 26) 227 #define DI_D3_CLK_POL (1 << 25) 228 #define DI_D3_DATA_POL (1 << 24) 229 230 /* DI_DISP_IF_CONF bits */ 231 #define DI_D3_CLK_IDLE (1 << 26) 232 #define DI_D3_CLK_SEL (1 << 25) 233 #define DI_D3_DATAMSK (1 << 24) 234 235 #define IOMUX_PADNUM_MASK 0x1ff 236 #define IOMUX_GPIONUM_SHIFT 9 237 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) 238 239 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) 240 241 #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) 242 243 struct chan_param_mem_planar { 244 /* Word 0 */ 245 u32 xv:10; 246 u32 yv:10; 247 u32 xb:12; 248 249 u32 yb:12; 250 u32 res1:2; 251 u32 nsb:1; 252 u32 lnpb:6; 253 u32 ubo_l:11; 254 255 u32 ubo_h:15; 256 u32 vbo_l:17; 257 258 u32 vbo_h:9; 259 u32 res2:3; 260 u32 fw:12; 261 u32 fh_l:8; 262 263 u32 fh_h:4; 264 u32 res3:28; 265 266 /* Word 1 */ 267 u32 eba0; 268 269 u32 eba1; 270 271 u32 bpp:3; 272 u32 sl:14; 273 u32 pfs:3; 274 u32 bam:3; 275 u32 res4:2; 276 u32 npb:6; 277 u32 res5:1; 278 279 u32 sat:2; 280 u32 res6:30; 281 } __attribute__ ((packed)); 282 283 struct chan_param_mem_interleaved { 284 /* Word 0 */ 285 u32 xv:10; 286 u32 yv:10; 287 u32 xb:12; 288 289 u32 yb:12; 290 u32 sce:1; 291 u32 res1:1; 292 u32 nsb:1; 293 u32 lnpb:6; 294 u32 sx:10; 295 u32 sy_l:1; 296 297 u32 sy_h:9; 298 u32 ns:10; 299 u32 sm:10; 300 u32 sdx_l:3; 301 302 u32 sdx_h:2; 303 u32 sdy:5; 304 u32 sdrx:1; 305 u32 sdry:1; 306 u32 sdr1:1; 307 u32 res2:2; 308 u32 fw:12; 309 u32 fh_l:8; 310 311 u32 fh_h:4; 312 u32 res3:28; 313 314 /* Word 1 */ 315 u32 eba0; 316 317 u32 eba1; 318 319 u32 bpp:3; 320 u32 sl:14; 321 u32 pfs:3; 322 u32 bam:3; 323 u32 res4:2; 324 u32 npb:6; 325 u32 res5:1; 326 327 u32 sat:2; 328 u32 scc:1; 329 u32 ofs0:5; 330 u32 ofs1:5; 331 u32 ofs2:5; 332 u32 ofs3:5; 333 u32 wid0:3; 334 u32 wid1:3; 335 u32 wid2:3; 336 337 u32 wid3:3; 338 u32 dec_sel:1; 339 u32 res6:28; 340 } __attribute__ ((packed)); 341 342 union chan_param_mem { 343 struct chan_param_mem_planar pp; 344 struct chan_param_mem_interleaved ip; 345 }; 346 347 DECLARE_GLOBAL_DATA_PTR; 348 349 /* graphics setup */ 350 static GraphicDevice panel; 351 static struct ctfb_res_modes *mode; 352 static struct ctfb_res_modes var_mode; 353 354 /* 355 * sdc_init_panel() - initialize a synchronous LCD panel. 356 * @width: width of panel in pixels. 357 * @height: height of panel in pixels. 358 * @di_setup: pixel format of the frame buffer 359 * @di_panel: either SHARP or normal TFT 360 * @return: 0 on success or negative error code on failure. 361 */ 362 static int sdc_init_panel(u16 width, u16 height, 363 enum pixel_fmt di_setup, enum ipu_panel di_panel) 364 { 365 u32 reg, div; 366 uint32_t old_conf; 367 int clock; 368 369 debug("%s(width=%d, height=%d)\n", __func__, width, height); 370 371 /* Init clocking, the IPU receives its clock from the hsp divder */ 372 clock = mxc_get_clock(MXC_IPU_CLK); 373 if (clock < 0) 374 return -EACCES; 375 376 /* Init panel size and blanking periods */ 377 reg = width + mode->left_margin + mode->right_margin - 1; 378 if (reg > 1023) { 379 printf("mx3fb: Display width too large, coerced to 1023!"); 380 reg = 1023; 381 } 382 reg = ((mode->hsync_len - 1) << 26) | (reg << 16); 383 writel(reg, SDC_HOR_CONF); 384 385 reg = height + mode->upper_margin + mode->lower_margin - 1; 386 if (reg > 1023) { 387 printf("mx3fb: Display height too large, coerced to 1023!"); 388 reg = 1023; 389 } 390 reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16); 391 writel(reg, SDC_VER_CONF); 392 393 switch (di_panel) { 394 case IPU_PANEL_SHARP_TFT: 395 writel(0x00FD0102L, SDC_SHARP_CONF_1); 396 writel(0x00F500F4L, SDC_SHARP_CONF_2); 397 writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); 398 /* TODO: probably IF_CONF must be adapted (see below)! */ 399 break; 400 case IPU_PANEL_TFT: 401 writel(SDC_COM_TFT_COLOR, SDC_COM_CONF); 402 break; 403 default: 404 return -EINVAL; 405 } 406 407 /* 408 * Calculate divider: The fractional part is 4 bits so simply 409 * multiple by 2^4 to get it. 410 * 411 * Opposed to the kernel driver mode->pixclock is the time of one 412 * pixel in pico seconds, so: 413 * pixel_clk = 1e12 / mode->pixclock 414 * div = ipu_clk * 16 / pixel_clk 415 * leads to: 416 * div = ipu_clk * 16 / (1e12 / mode->pixclock) 417 * or: 418 * div = ipu_clk * 16 * mode->pixclock / 1e12 419 * 420 * To avoid integer overflows this is split into 2 shifts and 421 * one divide with sufficient accuracy: 422 * 16*1024*128*476837 = 0.9999996682e12 423 */ 424 div = ((clock/1024) * (mode->pixclock/128)) / 476837; 425 debug("hsp_clk is %d, div=%d\n", clock, div); 426 /* coerce to not less than 4.0, not more than 255.9375 */ 427 if (div < 0x40) 428 div = 0x40; 429 else if (div > 0xFFF) 430 div = 0xFFF; 431 /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less 432 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR 433 * based on timing debug DISP3_IF_CLK_UP_WR is 0 434 */ 435 writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); 436 437 /* DI settings for display 3: clock idle (bit 26) during vsync */ 438 old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF; 439 writel(old_conf | IF_CONF, DI_DISP_IF_CONF); 440 441 /* only set display 3 polarity bits */ 442 old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF; 443 writel(old_conf | mode->sync, DI_DISP_SIG_POL); 444 445 writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP); 446 writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP); 447 writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP); 448 writel(readl(DI_DISP_ACC_CC) | 449 ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC); 450 451 debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF)); 452 debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL)); 453 debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF)); 454 debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF)); 455 debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF)); 456 457 return 0; 458 } 459 460 static void ipu_ch_param_set_size(union chan_param_mem *params, 461 uint pixelfmt, uint16_t width, 462 uint16_t height, uint16_t stride) 463 { 464 debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n", 465 __func__, pixelfmt, width, height, stride); 466 467 params->pp.fw = width - 1; 468 params->pp.fh_l = height - 1; 469 params->pp.fh_h = (height - 1) >> 8; 470 params->pp.sl = stride - 1; 471 472 /* See above, for further formats see the Linux driver */ 473 switch (pixelfmt) { 474 case GDF_16BIT_565RGB: 475 params->ip.bpp = 2; 476 params->ip.pfs = 4; 477 params->ip.npb = 7; 478 params->ip.sat = 2; /* SAT = 32-bit access */ 479 params->ip.ofs0 = 0; /* Red bit offset */ 480 params->ip.ofs1 = 5; /* Green bit offset */ 481 params->ip.ofs2 = 11; /* Blue bit offset */ 482 params->ip.ofs3 = 16; /* Alpha bit offset */ 483 params->ip.wid0 = 4; /* Red bit width - 1 */ 484 params->ip.wid1 = 5; /* Green bit width - 1 */ 485 params->ip.wid2 = 4; /* Blue bit width - 1 */ 486 break; 487 case GDF_32BIT_X888RGB: 488 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ 489 params->ip.pfs = 4; 490 params->ip.npb = 7; 491 params->ip.sat = 2; /* SAT = 32-bit access */ 492 params->ip.ofs0 = 16; /* Red bit offset */ 493 params->ip.ofs1 = 8; /* Green bit offset */ 494 params->ip.ofs2 = 0; /* Blue bit offset */ 495 params->ip.ofs3 = 24; /* Alpha bit offset */ 496 params->ip.wid0 = 7; /* Red bit width - 1 */ 497 params->ip.wid1 = 7; /* Green bit width - 1 */ 498 params->ip.wid2 = 7; /* Blue bit width - 1 */ 499 break; 500 default: 501 printf("mx3fb: Pixel format not supported!\n"); 502 break; 503 } 504 505 params->pp.nsb = 1; 506 } 507 508 static void ipu_ch_param_set_buffer(union chan_param_mem *params, 509 void *buf0, void *buf1) 510 { 511 params->pp.eba0 = (u32)buf0; 512 params->pp.eba1 = (u32)buf1; 513 } 514 515 static void ipu_write_param_mem(uint32_t addr, uint32_t *data, 516 uint32_t num_words) 517 { 518 for (; num_words > 0; num_words--) { 519 writel(addr, IPU_IMA_ADDR); 520 writel(*data++, IPU_IMA_DATA); 521 addr++; 522 if ((addr & 0x7) == 5) { 523 addr &= ~0x7; /* set to word 0 */ 524 addr += 8; /* increment to next row */ 525 } 526 } 527 } 528 529 static uint32_t dma_param_addr(enum ipu_channel channel) 530 { 531 /* Channel Parameter Memory */ 532 return 0x10000 | (channel << 4); 533 } 534 535 static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) 536 { 537 union chan_param_mem params = {}; 538 uint32_t reg; 539 uint32_t stride_bytes; 540 541 stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3; 542 543 debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem); 544 545 /* Build parameter memory data for DMA channel */ 546 ipu_ch_param_set_size(¶ms, panel.gdfIndex, 547 panel.plnSizeX, panel.plnSizeY, stride_bytes); 548 ipu_ch_param_set_buffer(¶ms, fbmem, NULL); 549 params.pp.bam = 0; 550 /* Some channels (rotation) have restriction on burst length */ 551 552 switch (channel) { 553 case IDMAC_SDC_0: 554 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ 555 params.pp.npb = 16 - 1; 556 break; 557 default: 558 break; 559 } 560 561 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); 562 563 /* Disable double-buffering */ 564 reg = readl(IPU_CHA_DB_MODE_SEL); 565 reg &= ~(1UL << channel); 566 writel(reg, IPU_CHA_DB_MODE_SEL); 567 } 568 569 static void ipu_channel_set_priority(enum ipu_channel channel, 570 int prio) 571 { 572 u32 reg = readl(IDMAC_CHA_PRI); 573 574 if (prio) 575 reg |= 1UL << channel; 576 else 577 reg &= ~(1UL << channel); 578 579 writel(reg, IDMAC_CHA_PRI); 580 } 581 582 /* 583 * ipu_enable_channel() - enable an IPU channel. 584 * @channel: channel ID. 585 * @return: 0 on success or negative error code on failure. 586 */ 587 static int ipu_enable_channel(enum ipu_channel channel) 588 { 589 uint32_t reg; 590 591 /* Reset to buffer 0 */ 592 writel(1UL << channel, IPU_CHA_CUR_BUF); 593 594 switch (channel) { 595 case IDMAC_SDC_0: 596 ipu_channel_set_priority(channel, 1); 597 break; 598 default: 599 break; 600 } 601 602 reg = readl(IDMAC_CHA_EN); 603 writel(reg | (1UL << channel), IDMAC_CHA_EN); 604 605 return 0; 606 } 607 608 static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) 609 { 610 uint32_t reg; 611 612 reg = readl(IPU_CHA_BUF0_RDY); 613 if (reg & (1UL << channel)) 614 return -EACCES; 615 616 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ 617 writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); 618 writel((u32)buf, IPU_IMA_DATA); 619 620 return 0; 621 } 622 623 static int idmac_tx_submit(enum ipu_channel channel, void *buf) 624 { 625 int ret; 626 627 ipu_init_channel_buffer(channel, buf); 628 629 630 /* ipu_idmac.c::ipu_submit_channel_buffers() */ 631 ret = ipu_update_channel_buffer(channel, buf); 632 if (ret < 0) 633 return ret; 634 635 /* ipu_idmac.c::ipu_select_buffer() */ 636 /* Mark buffer 0 as ready. */ 637 writel(1UL << channel, IPU_CHA_BUF0_RDY); 638 639 640 ret = ipu_enable_channel(channel); 641 return ret; 642 } 643 644 static void sdc_enable_channel(void *fbmem) 645 { 646 int ret; 647 u32 reg; 648 649 ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); 650 651 /* mx3fb.c::sdc_fb_init() */ 652 if (ret >= 0) { 653 reg = readl(SDC_COM_CONF); 654 writel(reg | SDC_COM_BG_EN, SDC_COM_CONF); 655 } 656 657 /* 658 * Attention! Without this msleep the channel keeps generating 659 * interrupts. Next sdc_set_brightness() is going to be called 660 * from mx3fb_blank(). 661 */ 662 udelay(2000); 663 } 664 665 /* 666 * mx3fb_set_par() - set framebuffer parameters and change the operating mode. 667 * @return: 0 on success or negative error code on failure. 668 * TODO: currently only 666 and TFT as DI setup supported 669 */ 670 static int mx3fb_set_par(void) 671 { 672 int ret; 673 674 ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY, 675 IPU_PIX_FMT_RGB666, IPU_PANEL_TFT); 676 if (ret < 0) 677 return ret; 678 679 writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS); 680 681 return 0; 682 } 683 684 static void ll_disp3_enable(void *base) 685 { 686 u32 reg; 687 688 debug("%s(base=0x%x)\n", __func__, (u32) base); 689 /* pcm037.c::mxc_board_init() */ 690 691 /* Display Interface #3 */ 692 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); 693 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); 694 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); 695 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); 696 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); 697 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); 698 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); 699 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); 700 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); 701 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); 702 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); 703 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); 704 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); 705 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); 706 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); 707 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); 708 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); 709 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); 710 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); 711 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); 712 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); 713 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); 714 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); 715 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); 716 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); 717 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); 718 719 720 /* ipu_idmac.c::ipu_probe() */ 721 722 /* Start the clock */ 723 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); 724 725 726 /* ipu_idmac.c::ipu_idmac_init() */ 727 728 /* Service request counter to maximum - shouldn't be needed */ 729 writel(0x00000070, IDMAC_CONF); 730 731 732 /* ipu_idmac.c::ipu_init_channel() */ 733 734 /* Enable IPU sub modules */ 735 reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; 736 writel(reg, IPU_CONF); 737 738 739 /* mx3fb.c::init_fb_chan() */ 740 741 /* set Display Interface clock period */ 742 writel(0x00100010L, DI_HSP_CLK_PER); 743 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ 744 745 746 /* mx3fb.c::sdc_set_brightness() */ 747 748 /* This might be board-specific */ 749 writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL); 750 751 752 /* mx3fb.c::sdc_set_global_alpha() */ 753 754 /* Use global - not per-pixel - Alpha-blending */ 755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; 756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); 757 758 reg = readl(SDC_COM_CONF); 759 writel(reg | SDC_COM_GLB_A, SDC_COM_CONF); 760 761 762 /* mx3fb.c::sdc_set_color_key() */ 763 764 /* Disable colour-keying for background */ 765 reg = readl(SDC_COM_CONF) & 766 ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); 767 writel(reg, SDC_COM_CONF); 768 769 770 mx3fb_set_par(); 771 772 sdc_enable_channel(base); 773 774 /* 775 * Linux driver calls sdc_set_brightness() here again, 776 * once is enough for us 777 */ 778 debug("%s() done\n", __func__); 779 } 780 781 /* ------------------------ public part ------------------- */ 782 ulong calc_fbsize(void) 783 { 784 return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP; 785 } 786 787 /* 788 * The current implementation is only tested for GDF_16BIT_565RGB! 789 * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO, 790 * because the lcd code seemed loaded with color table stuff, that 791 * does not relate to most modern TFTs. cfb_console.c looks more 792 * straight forward. 793 * This is the environment setting for the original setup 794 * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17, 795 * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0" 796 * "videomode=unknown" 797 * 798 * Settings for VBEST VGG322403 display: 799 * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000, 800 * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0" 801 * 802 * Settings for COM57H5M10XRC display: 803 * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000, 804 * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0" 805 */ 806 void *video_hw_init(void) 807 { 808 char *penv; 809 u32 memsize; 810 unsigned long t1, hsynch, vsynch; 811 int bits_per_pixel, i, tmp, videomode; 812 813 tmp = 0; 814 815 puts("Video: "); 816 817 videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; 818 /* get video mode via environment */ 819 penv = env_get("videomode"); 820 if (penv) { 821 /* decide if it is a string */ 822 if (penv[0] <= '9') { 823 videomode = (int) simple_strtoul(penv, NULL, 16); 824 tmp = 1; 825 } 826 } else { 827 tmp = 1; 828 } 829 if (tmp) { 830 /* parameter are vesa modes */ 831 /* search params */ 832 for (i = 0; i < VESA_MODES_COUNT; i++) { 833 if (vesa_modes[i].vesanr == videomode) 834 break; 835 } 836 if (i == VESA_MODES_COUNT) { 837 printf("No VESA Mode found, switching to mode 0x%x ", 838 CONFIG_SYS_DEFAULT_VIDEO_MODE); 839 i = 0; 840 } 841 mode = (struct ctfb_res_modes *) 842 &res_mode_init[vesa_modes[i].resindex]; 843 bits_per_pixel = vesa_modes[i].bits_per_pixel; 844 } else { 845 mode = (struct ctfb_res_modes *) &var_mode; 846 bits_per_pixel = video_get_params(mode, penv); 847 } 848 849 /* calculate hsynch and vsynch freq (info only) */ 850 t1 = (mode->left_margin + mode->xres + 851 mode->right_margin + mode->hsync_len) / 8; 852 t1 *= 8; 853 t1 *= mode->pixclock; 854 t1 /= 1000; 855 hsynch = 1000000000L / t1; 856 t1 *= (mode->upper_margin + mode->yres + 857 mode->lower_margin + mode->vsync_len); 858 t1 /= 1000; 859 vsynch = 1000000000L / t1; 860 861 /* fill in Graphic device struct */ 862 sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz", 863 mode->xres, mode->yres, 864 bits_per_pixel, (hsynch / 1000), (vsynch / 1000)); 865 printf("%s\n", panel.modeIdent); 866 panel.winSizeX = mode->xres; 867 panel.winSizeY = mode->yres; 868 panel.plnSizeX = mode->xres; 869 panel.plnSizeY = mode->yres; 870 871 switch (bits_per_pixel) { 872 case 24: 873 panel.gdfBytesPP = 4; 874 panel.gdfIndex = GDF_32BIT_X888RGB; 875 break; 876 case 16: 877 panel.gdfBytesPP = 2; 878 panel.gdfIndex = GDF_16BIT_565RGB; 879 break; 880 default: 881 panel.gdfBytesPP = 1; 882 panel.gdfIndex = GDF__8BIT_INDEX; 883 break; 884 } 885 886 /* set up Hardware */ 887 memsize = calc_fbsize(); 888 889 debug("%s() allocating %d bytes\n", __func__, memsize); 890 891 /* fill in missing Graphic device struct */ 892 panel.frameAdrs = (u32) malloc(memsize); 893 if (panel.frameAdrs == 0) { 894 printf("%s() malloc(%d) failed\n", __func__, memsize); 895 return 0; 896 } 897 panel.memSize = memsize; 898 899 ll_disp3_enable((void *) panel.frameAdrs); 900 memset((void *) panel.frameAdrs, 0, memsize); 901 902 debug("%s() done, framebuffer at 0x%x, size=%d cleared\n", 903 __func__, panel.frameAdrs, memsize); 904 905 return (void *) &panel; 906 } 907