1 /* 2 * Copyright (C) 2009 3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <lcd.h> 25 #include <asm/arch/mx31.h> 26 #include <asm/arch/mx31-regs.h> 27 #include <asm/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 void *lcd_base; /* Start of framebuffer memory */ 32 void *lcd_console_address; /* Start of console buffer */ 33 34 int lcd_line_length; 35 int lcd_color_fg; 36 int lcd_color_bg; 37 38 short console_col; 39 short console_row; 40 41 void lcd_initcolregs(void) 42 { 43 } 44 45 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 46 { 47 } 48 49 void lcd_disable(void) 50 { 51 } 52 53 void lcd_panel_disable(void) 54 { 55 } 56 57 #define msleep(a) udelay(a * 1000) 58 59 #ifndef CONFIG_DISPLAY_VBEST_VGG322403 60 #define XRES 240 61 #define YRES 320 62 #define PANEL_TYPE IPU_PANEL_TFT 63 #define PIXEL_CLK 185925 64 #define PIXEL_FMT IPU_PIX_FMT_RGB666 65 #define H_START_WIDTH 9 /* left_margin */ 66 #define H_SYNC_WIDTH 1 /* hsync_len */ 67 #define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ 68 #define V_START_WIDTH 7 /* upper_margin */ 69 #define V_SYNC_WIDTH 1 /* vsync_len */ 70 #define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ 71 #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) 72 #define IF_CONF 0 73 #define IF_CLK_DIV 0x175 74 #else /* Display Vbest VGG322403 */ 75 #define XRES 320 76 #define YRES 240 77 #define PANEL_TYPE IPU_PANEL_TFT 78 #define PIXEL_CLK 156000 79 #define PIXEL_FMT IPU_PIX_FMT_RGB666 80 #define H_START_WIDTH 20 /* left_margin */ 81 #define H_SYNC_WIDTH 30 /* hsync_len */ 82 #define H_END_WIDTH (38 + 30) /* right_margin + hsync_len */ 83 #define V_START_WIDTH 7 /* upper_margin */ 84 #define V_SYNC_WIDTH 3 /* vsync_len */ 85 #define V_END_WIDTH (26 + 3) /* lower_margin + vsync_len */ 86 #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) 87 #define IF_CONF 0 88 #define IF_CLK_DIV 0x175 89 #endif 90 91 #define LCD_COLOR_IPU LCD_COLOR16 92 93 static ushort colormap[256]; 94 95 vidinfo_t panel_info = { 96 .vl_col = XRES, 97 .vl_row = YRES, 98 .vl_bpix = LCD_COLOR_IPU, 99 .cmap = colormap, 100 }; 101 102 #define BIT_PER_PIXEL NBITS(LCD_COLOR_IPU) 103 104 /* IPU DMA Controller channel definitions. */ 105 enum ipu_channel { 106 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ 107 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ 108 IDMAC_ADC_0 = 1, 109 IDMAC_IC_2 = 2, 110 IDMAC_ADC_1 = 2, 111 IDMAC_IC_3 = 3, 112 IDMAC_IC_4 = 4, 113 IDMAC_IC_5 = 5, 114 IDMAC_IC_6 = 6, 115 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ 116 IDMAC_IC_8 = 8, 117 IDMAC_IC_9 = 9, 118 IDMAC_IC_10 = 10, 119 IDMAC_IC_11 = 11, 120 IDMAC_IC_12 = 12, 121 IDMAC_IC_13 = 13, 122 IDMAC_SDC_0 = 14, /* Background synchronous display data */ 123 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ 124 IDMAC_SDC_2 = 16, 125 IDMAC_SDC_3 = 17, 126 IDMAC_ADC_2 = 18, 127 IDMAC_ADC_3 = 19, 128 IDMAC_ADC_4 = 20, 129 IDMAC_ADC_5 = 21, 130 IDMAC_ADC_6 = 22, 131 IDMAC_ADC_7 = 23, 132 IDMAC_PF_0 = 24, 133 IDMAC_PF_1 = 25, 134 IDMAC_PF_2 = 26, 135 IDMAC_PF_3 = 27, 136 IDMAC_PF_4 = 28, 137 IDMAC_PF_5 = 29, 138 IDMAC_PF_6 = 30, 139 IDMAC_PF_7 = 31, 140 }; 141 142 /* More formats can be copied from the Linux driver if needed */ 143 enum pixel_fmt { 144 /* 2 bytes */ 145 IPU_PIX_FMT_RGB565, 146 IPU_PIX_FMT_RGB666, 147 IPU_PIX_FMT_BGR666, 148 /* 3 bytes */ 149 IPU_PIX_FMT_RGB24, 150 }; 151 152 struct pixel_fmt_cfg { 153 u32 b0; 154 u32 b1; 155 u32 b2; 156 u32 acc; 157 }; 158 159 static struct pixel_fmt_cfg fmt_cfg[] = { 160 [IPU_PIX_FMT_RGB24] = { 161 0x1600AAAA, 0x00E05555, 0x00070000, 3, 162 }, 163 [IPU_PIX_FMT_RGB666] = { 164 0x0005000F, 0x000B000F, 0x0011000F, 1, 165 }, 166 [IPU_PIX_FMT_BGR666] = { 167 0x0011000F, 0x000B000F, 0x0005000F, 1, 168 }, 169 [IPU_PIX_FMT_RGB565] = { 170 0x0004003F, 0x000A000F, 0x000F003F, 1, 171 } 172 }; 173 174 enum ipu_panel { 175 IPU_PANEL_SHARP_TFT, 176 IPU_PANEL_TFT, 177 }; 178 179 /* IPU Common registers */ 180 /* IPU_CONF and its bits already defined in mx31-regs.h */ 181 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) 182 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) 183 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) 184 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) 185 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) 186 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) 187 #define IPU_TASKS_STAT (0x1C + IPU_BASE) 188 #define IPU_IMA_ADDR (0x20 + IPU_BASE) 189 #define IPU_IMA_DATA (0x24 + IPU_BASE) 190 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE) 191 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE) 192 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE) 193 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE) 194 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE) 195 #define IPU_INT_STAT_1 (0x3C + IPU_BASE) 196 #define IPU_INT_STAT_2 (0x40 + IPU_BASE) 197 #define IPU_INT_STAT_3 (0x44 + IPU_BASE) 198 #define IPU_INT_STAT_4 (0x48 + IPU_BASE) 199 #define IPU_INT_STAT_5 (0x4C + IPU_BASE) 200 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) 201 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) 202 #define IPU_BRK_STAT (0x58 + IPU_BASE) 203 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE) 204 205 /* Image Converter Registers */ 206 #define IC_CONF (0x88 + IPU_BASE) 207 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE) 208 #define IC_PRP_VF_RSC (0x90 + IPU_BASE) 209 #define IC_PP_RSC (0x94 + IPU_BASE) 210 #define IC_CMBP_1 (0x98 + IPU_BASE) 211 #define IC_CMBP_2 (0x9C + IPU_BASE) 212 #define PF_CONF (0xA0 + IPU_BASE) 213 #define IDMAC_CONF (0xA4 + IPU_BASE) 214 #define IDMAC_CHA_EN (0xA8 + IPU_BASE) 215 #define IDMAC_CHA_PRI (0xAC + IPU_BASE) 216 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) 217 218 /* Image Converter Register bits */ 219 #define IC_CONF_PRPENC_EN 0x00000001 220 #define IC_CONF_PRPENC_CSC1 0x00000002 221 #define IC_CONF_PRPENC_ROT_EN 0x00000004 222 #define IC_CONF_PRPVF_EN 0x00000100 223 #define IC_CONF_PRPVF_CSC1 0x00000200 224 #define IC_CONF_PRPVF_CSC2 0x00000400 225 #define IC_CONF_PRPVF_CMB 0x00000800 226 #define IC_CONF_PRPVF_ROT_EN 0x00001000 227 #define IC_CONF_PP_EN 0x00010000 228 #define IC_CONF_PP_CSC1 0x00020000 229 #define IC_CONF_PP_CSC2 0x00040000 230 #define IC_CONF_PP_CMB 0x00080000 231 #define IC_CONF_PP_ROT_EN 0x00100000 232 #define IC_CONF_IC_GLB_LOC_A 0x10000000 233 #define IC_CONF_KEY_COLOR_EN 0x20000000 234 #define IC_CONF_RWS_EN 0x40000000 235 #define IC_CONF_CSI_MEM_WR_EN 0x80000000 236 237 /* SDC Registers */ 238 #define SDC_COM_CONF (0xB4 + IPU_BASE) 239 #define SDC_GW_CTRL (0xB8 + IPU_BASE) 240 #define SDC_FG_POS (0xBC + IPU_BASE) 241 #define SDC_BG_POS (0xC0 + IPU_BASE) 242 #define SDC_CUR_POS (0xC4 + IPU_BASE) 243 #define SDC_PWM_CTRL (0xC8 + IPU_BASE) 244 #define SDC_CUR_MAP (0xCC + IPU_BASE) 245 #define SDC_HOR_CONF (0xD0 + IPU_BASE) 246 #define SDC_VER_CONF (0xD4 + IPU_BASE) 247 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) 248 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) 249 250 /* Register bits */ 251 #define SDC_COM_TFT_COLOR 0x00000001UL 252 #define SDC_COM_FG_EN 0x00000010UL 253 #define SDC_COM_GWSEL 0x00000020UL 254 #define SDC_COM_GLB_A 0x00000040UL 255 #define SDC_COM_KEY_COLOR_G 0x00000080UL 256 #define SDC_COM_BG_EN 0x00000200UL 257 #define SDC_COM_SHARP 0x00001000UL 258 259 #define SDC_V_SYNC_WIDTH_L 0x00000001UL 260 261 /* Display Interface registers */ 262 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE) 263 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE) 264 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE) 265 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) 266 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE) 267 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) 268 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) 269 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) 270 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) 271 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) 272 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) 273 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) 274 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) 275 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) 276 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) 277 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) 278 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) 279 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) 280 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) 281 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) 282 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) 283 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) 284 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) 285 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) 286 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) 287 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) 288 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) 289 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) 290 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) 291 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) 292 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) 293 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) 294 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) 295 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) 296 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) 297 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) 298 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) 299 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) 300 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) 301 302 /* DI_DISP_SIG_POL bits */ 303 #define DI_D3_VSYNC_POL (1 << 28) 304 #define DI_D3_HSYNC_POL (1 << 27) 305 #define DI_D3_DRDY_SHARP_POL (1 << 26) 306 #define DI_D3_CLK_POL (1 << 25) 307 #define DI_D3_DATA_POL (1 << 24) 308 309 /* DI_DISP_IF_CONF bits */ 310 #define DI_D3_CLK_IDLE (1 << 26) 311 #define DI_D3_CLK_SEL (1 << 25) 312 #define DI_D3_DATAMSK (1 << 24) 313 314 #define IOMUX_PADNUM_MASK 0x1ff 315 #define IOMUX_GPIONUM_SHIFT 9 316 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) 317 318 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) 319 320 #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) 321 322 enum lcd_pin { 323 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), 324 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), 325 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), 326 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), 327 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), 328 329 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), 330 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), 331 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), 332 333 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), 334 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), 335 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), 336 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), 337 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), 338 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), 339 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), 340 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), 341 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), 342 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), 343 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), 344 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), 345 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), 346 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), 347 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), 348 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), 349 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), 350 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), 351 }; 352 353 struct chan_param_mem_planar { 354 /* Word 0 */ 355 u32 xv:10; 356 u32 yv:10; 357 u32 xb:12; 358 359 u32 yb:12; 360 u32 res1:2; 361 u32 nsb:1; 362 u32 lnpb:6; 363 u32 ubo_l:11; 364 365 u32 ubo_h:15; 366 u32 vbo_l:17; 367 368 u32 vbo_h:9; 369 u32 res2:3; 370 u32 fw:12; 371 u32 fh_l:8; 372 373 u32 fh_h:4; 374 u32 res3:28; 375 376 /* Word 1 */ 377 u32 eba0; 378 379 u32 eba1; 380 381 u32 bpp:3; 382 u32 sl:14; 383 u32 pfs:3; 384 u32 bam:3; 385 u32 res4:2; 386 u32 npb:6; 387 u32 res5:1; 388 389 u32 sat:2; 390 u32 res6:30; 391 } __attribute__ ((packed)); 392 393 struct chan_param_mem_interleaved { 394 /* Word 0 */ 395 u32 xv:10; 396 u32 yv:10; 397 u32 xb:12; 398 399 u32 yb:12; 400 u32 sce:1; 401 u32 res1:1; 402 u32 nsb:1; 403 u32 lnpb:6; 404 u32 sx:10; 405 u32 sy_l:1; 406 407 u32 sy_h:9; 408 u32 ns:10; 409 u32 sm:10; 410 u32 sdx_l:3; 411 412 u32 sdx_h:2; 413 u32 sdy:5; 414 u32 sdrx:1; 415 u32 sdry:1; 416 u32 sdr1:1; 417 u32 res2:2; 418 u32 fw:12; 419 u32 fh_l:8; 420 421 u32 fh_h:4; 422 u32 res3:28; 423 424 /* Word 1 */ 425 u32 eba0; 426 427 u32 eba1; 428 429 u32 bpp:3; 430 u32 sl:14; 431 u32 pfs:3; 432 u32 bam:3; 433 u32 res4:2; 434 u32 npb:6; 435 u32 res5:1; 436 437 u32 sat:2; 438 u32 scc:1; 439 u32 ofs0:5; 440 u32 ofs1:5; 441 u32 ofs2:5; 442 u32 ofs3:5; 443 u32 wid0:3; 444 u32 wid1:3; 445 u32 wid2:3; 446 447 u32 wid3:3; 448 u32 dec_sel:1; 449 u32 res6:28; 450 } __attribute__ ((packed)); 451 452 union chan_param_mem { 453 struct chan_param_mem_planar pp; 454 struct chan_param_mem_interleaved ip; 455 }; 456 457 static inline u32 reg_read(unsigned long reg) 458 { 459 return __REG(reg); 460 } 461 462 static inline void reg_write(u32 value, unsigned long reg) 463 { 464 __REG(reg) = value; 465 } 466 467 /* 468 * sdc_init_panel() - initialize a synchronous LCD panel. 469 * @width: width of panel in pixels. 470 * @height: height of panel in pixels. 471 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. 472 * @return: 0 on success or negative error code on failure. 473 */ 474 static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt) 475 { 476 u32 reg; 477 uint32_t old_conf; 478 479 /* Init panel size and blanking periods */ 480 reg = ((H_SYNC_WIDTH - 1) << 26) | 481 ((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16); 482 reg_write(reg, SDC_HOR_CONF); 483 484 reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L | 485 ((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16); 486 reg_write(reg, SDC_VER_CONF); 487 488 switch (PANEL_TYPE) { 489 case IPU_PANEL_SHARP_TFT: 490 reg_write(0x00FD0102L, SDC_SHARP_CONF_1); 491 reg_write(0x00F500F4L, SDC_SHARP_CONF_2); 492 reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); 493 break; 494 case IPU_PANEL_TFT: 495 reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF); 496 break; 497 default: 498 return -EINVAL; 499 } 500 501 /* Init clocking */ 502 503 /* 504 * Calculate divider: fractional part is 4 bits so simply multiple by 505 * 2^4 to get fractional part, as long as we stay under ~250MHz and on 506 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz 507 */ 508 509 reg_write((((IF_CLK_DIV / 8) - 1) << 22) | 510 IF_CLK_DIV, DI_DISP3_TIME_CONF); 511 512 /* DI settings */ 513 old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF; 514 reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF); 515 516 old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF; 517 reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL); 518 519 reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP); 520 reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP); 521 reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP); 522 reg_write(reg_read(DI_DISP_ACC_CC) | 523 ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC); 524 525 return 0; 526 } 527 528 static void ipu_ch_param_set_size(union chan_param_mem *params, 529 uint32_t pixel_fmt, uint16_t width, 530 uint16_t height, uint16_t stride) 531 { 532 params->pp.fw = width - 1; 533 params->pp.fh_l = height - 1; 534 params->pp.fh_h = (height - 1) >> 8; 535 params->pp.sl = stride - 1; 536 537 /* See above, for further formats see the Linux driver */ 538 switch (pixel_fmt) { 539 case IPU_PIX_FMT_RGB565: 540 params->ip.bpp = 2; 541 params->ip.pfs = 4; 542 params->ip.npb = 7; 543 params->ip.sat = 2; /* SAT = 32-bit access */ 544 params->ip.ofs0 = 0; /* Red bit offset */ 545 params->ip.ofs1 = 5; /* Green bit offset */ 546 params->ip.ofs2 = 11; /* Blue bit offset */ 547 params->ip.ofs3 = 16; /* Alpha bit offset */ 548 params->ip.wid0 = 4; /* Red bit width - 1 */ 549 params->ip.wid1 = 5; /* Green bit width - 1 */ 550 params->ip.wid2 = 4; /* Blue bit width - 1 */ 551 break; 552 case IPU_PIX_FMT_RGB24: 553 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ 554 params->ip.pfs = 4; 555 params->ip.npb = 7; 556 params->ip.sat = 2; /* SAT = 32-bit access */ 557 params->ip.ofs0 = 16; /* Red bit offset */ 558 params->ip.ofs1 = 8; /* Green bit offset */ 559 params->ip.ofs2 = 0; /* Blue bit offset */ 560 params->ip.ofs3 = 24; /* Alpha bit offset */ 561 params->ip.wid0 = 7; /* Red bit width - 1 */ 562 params->ip.wid1 = 7; /* Green bit width - 1 */ 563 params->ip.wid2 = 7; /* Blue bit width - 1 */ 564 break; 565 default: 566 break; 567 } 568 569 params->pp.nsb = 1; 570 } 571 572 static void ipu_ch_param_set_buffer(union chan_param_mem *params, 573 void *buf0, void *buf1) 574 { 575 params->pp.eba0 = (u32)buf0; 576 params->pp.eba1 = (u32)buf1; 577 } 578 579 static void ipu_write_param_mem(uint32_t addr, uint32_t *data, 580 uint32_t num_words) 581 { 582 for (; num_words > 0; num_words--) { 583 reg_write(addr, IPU_IMA_ADDR); 584 reg_write(*data++, IPU_IMA_DATA); 585 addr++; 586 if ((addr & 0x7) == 5) { 587 addr &= ~0x7; /* set to word 0 */ 588 addr += 8; /* increment to next row */ 589 } 590 } 591 } 592 593 static uint32_t bpp_to_pixfmt(int bpp) 594 { 595 switch (bpp) { 596 case 16: 597 return IPU_PIX_FMT_RGB565; 598 default: 599 return 0; 600 } 601 } 602 603 static uint32_t dma_param_addr(enum ipu_channel channel) 604 { 605 /* Channel Parameter Memory */ 606 return 0x10000 | (channel << 4); 607 } 608 609 static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) 610 { 611 union chan_param_mem params = {}; 612 uint32_t reg; 613 uint32_t stride_bytes; 614 615 stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3; 616 617 /* Build parameter memory data for DMA channel */ 618 ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(BIT_PER_PIXEL), 619 XRES, YRES, stride_bytes); 620 ipu_ch_param_set_buffer(¶ms, fbmem, NULL); 621 params.pp.bam = 0; 622 /* Some channels (rotation) have restriction on burst length */ 623 624 switch (channel) { 625 case IDMAC_SDC_0: 626 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ 627 params.pp.npb = 16 - 1; 628 break; 629 default: 630 break; 631 } 632 633 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); 634 635 /* Disable double-buffering */ 636 reg = reg_read(IPU_CHA_DB_MODE_SEL); 637 reg &= ~(1UL << channel); 638 reg_write(reg, IPU_CHA_DB_MODE_SEL); 639 } 640 641 static void ipu_channel_set_priority(enum ipu_channel channel, 642 int prio) 643 { 644 u32 reg = reg_read(IDMAC_CHA_PRI); 645 646 if (prio) 647 reg |= 1UL << channel; 648 else 649 reg &= ~(1UL << channel); 650 651 reg_write(reg, IDMAC_CHA_PRI); 652 } 653 654 /* 655 * ipu_enable_channel() - enable an IPU channel. 656 * @channel: channel ID. 657 * @return: 0 on success or negative error code on failure. 658 */ 659 static int ipu_enable_channel(enum ipu_channel channel) 660 { 661 uint32_t reg; 662 663 /* Reset to buffer 0 */ 664 reg_write(1UL << channel, IPU_CHA_CUR_BUF); 665 666 switch (channel) { 667 case IDMAC_SDC_0: 668 ipu_channel_set_priority(channel, 1); 669 break; 670 default: 671 break; 672 } 673 674 reg = reg_read(IDMAC_CHA_EN); 675 reg_write(reg | (1UL << channel), IDMAC_CHA_EN); 676 677 return 0; 678 } 679 680 static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) 681 { 682 uint32_t reg; 683 684 reg = reg_read(IPU_CHA_BUF0_RDY); 685 if (reg & (1UL << channel)) 686 return -EACCES; 687 688 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ 689 reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); 690 reg_write((u32)buf, IPU_IMA_DATA); 691 692 return 0; 693 } 694 695 static int idmac_tx_submit(enum ipu_channel channel, void *buf) 696 { 697 int ret; 698 699 ipu_init_channel_buffer(channel, buf); 700 701 702 /* ipu_idmac.c::ipu_submit_channel_buffers() */ 703 ret = ipu_update_channel_buffer(channel, buf); 704 if (ret < 0) 705 return ret; 706 707 /* ipu_idmac.c::ipu_select_buffer() */ 708 /* Mark buffer 0 as ready. */ 709 reg_write(1UL << channel, IPU_CHA_BUF0_RDY); 710 711 712 ret = ipu_enable_channel(channel); 713 return ret; 714 } 715 716 static void sdc_enable_channel(void *fbmem) 717 { 718 int ret; 719 u32 reg; 720 721 ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); 722 723 /* mx3fb.c::sdc_fb_init() */ 724 if (ret >= 0) { 725 reg = reg_read(SDC_COM_CONF); 726 reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF); 727 } 728 729 /* 730 * Attention! Without this msleep the channel keeps generating 731 * interrupts. Next sdc_set_brightness() is going to be called 732 * from mx3fb_blank(). 733 */ 734 msleep(2); 735 } 736 737 /* 738 * mx3fb_set_par() - set framebuffer parameters and change the operating mode. 739 * @return: 0 on success or negative error code on failure. 740 */ 741 static int mx3fb_set_par(void) 742 { 743 int ret; 744 745 ret = sdc_init_panel(XRES, YRES, PIXEL_FMT); 746 if (ret < 0) 747 return ret; 748 749 reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS); 750 751 return 0; 752 } 753 754 /* References in this function refer to respective Linux kernel sources */ 755 void lcd_enable(void) 756 { 757 u32 reg; 758 759 /* pcm037.c::mxc_board_init() */ 760 761 /* Display Interface #3 */ 762 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); 763 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); 764 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); 765 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); 766 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); 767 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); 768 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); 769 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); 770 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); 771 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); 772 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); 773 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); 774 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); 775 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); 776 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); 777 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); 778 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); 779 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); 780 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); 781 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); 782 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); 783 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); 784 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); 785 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); 786 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); 787 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); 788 789 790 /* ipu_idmac.c::ipu_probe() */ 791 792 /* Start the clock */ 793 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); 794 795 796 /* ipu_idmac.c::ipu_idmac_init() */ 797 798 /* Service request counter to maximum - shouldn't be needed */ 799 reg_write(0x00000070, IDMAC_CONF); 800 801 802 /* ipu_idmac.c::ipu_init_channel() */ 803 804 /* Enable IPU sub modules */ 805 reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; 806 reg_write(reg, IPU_CONF); 807 808 809 /* mx3fb.c::init_fb_chan() */ 810 811 /* set Display Interface clock period */ 812 reg_write(0x00100010L, DI_HSP_CLK_PER); 813 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ 814 815 816 /* mx3fb.c::sdc_set_brightness() */ 817 818 /* This might be board-specific */ 819 reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL); 820 821 822 /* mx3fb.c::sdc_set_global_alpha() */ 823 824 /* Use global - not per-pixel - Alpha-blending */ 825 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; 826 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); 827 828 reg = reg_read(SDC_COM_CONF); 829 reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF); 830 831 832 /* mx3fb.c::sdc_set_color_key() */ 833 834 /* Disable colour-keying for background */ 835 reg = reg_read(SDC_COM_CONF) & 836 ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); 837 reg_write(reg, SDC_COM_CONF); 838 839 840 mx3fb_set_par(); 841 842 sdc_enable_channel(lcd_base); 843 844 /* 845 * Linux driver calls sdc_set_brightness() here again, 846 * once is enough for us 847 */ 848 } 849 850 void lcd_ctrl_init(void *lcdbase) 851 { 852 u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8; 853 /* 854 * We rely on lcdbase being a physical address, i.e., either MMU off, 855 * or 1-to-1 mapping. Might want to add some virt2phys here. 856 */ 857 if (!lcdbase) 858 return; 859 860 memset(lcdbase, 0, mem_len); 861 } 862 863 ulong calc_fbsize(void) 864 { 865 return ((panel_info.vl_col * panel_info.vl_row * 866 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; 867 } 868 869 int overwrite_console(void) 870 { 871 /* Keep stdout / stderr on serial, our LCD is for splashscreen only */ 872 return 1; 873 } 874