1 /* 2 * Copyright (C) 2009 3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <lcd.h> 25 #include <asm/arch/mx31.h> 26 #include <asm/arch/mx31-regs.h> 27 #include <asm/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 void *lcd_base; /* Start of framebuffer memory */ 32 void *lcd_console_address; /* Start of console buffer */ 33 34 int lcd_line_length; 35 int lcd_color_fg; 36 int lcd_color_bg; 37 38 short console_col; 39 short console_row; 40 41 void lcd_initcolregs(void) 42 { 43 } 44 45 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 46 { 47 } 48 49 void lcd_disable(void) 50 { 51 } 52 53 void lcd_panel_disable(void) 54 { 55 } 56 57 #define msleep(a) udelay(a * 1000) 58 59 #define XRES 240 60 #define YRES 320 61 #define PANEL_TYPE IPU_PANEL_TFT 62 #define PIXEL_CLK 185925 63 #define PIXEL_FMT IPU_PIX_FMT_RGB666 64 #define H_START_WIDTH 9 /* left_margin */ 65 #define H_SYNC_WIDTH 1 /* hsync_len */ 66 #define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ 67 #define V_START_WIDTH 7 /* upper_margin */ 68 #define V_SYNC_WIDTH 1 /* vsync_len */ 69 #define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ 70 #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) 71 #define IF_CONF 0 72 #define IF_CLK_DIV 0x175 73 74 #define LCD_COLOR_IPU LCD_COLOR16 75 76 static ushort colormap[256]; 77 78 vidinfo_t panel_info = { 79 .vl_col = XRES, 80 .vl_row = YRES, 81 .vl_bpix = LCD_COLOR_IPU, 82 .cmap = colormap, 83 }; 84 85 #define BIT_PER_PIXEL NBITS(LCD_COLOR_IPU) 86 87 /* IPU DMA Controller channel definitions. */ 88 enum ipu_channel { 89 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ 90 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ 91 IDMAC_ADC_0 = 1, 92 IDMAC_IC_2 = 2, 93 IDMAC_ADC_1 = 2, 94 IDMAC_IC_3 = 3, 95 IDMAC_IC_4 = 4, 96 IDMAC_IC_5 = 5, 97 IDMAC_IC_6 = 6, 98 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ 99 IDMAC_IC_8 = 8, 100 IDMAC_IC_9 = 9, 101 IDMAC_IC_10 = 10, 102 IDMAC_IC_11 = 11, 103 IDMAC_IC_12 = 12, 104 IDMAC_IC_13 = 13, 105 IDMAC_SDC_0 = 14, /* Background synchronous display data */ 106 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ 107 IDMAC_SDC_2 = 16, 108 IDMAC_SDC_3 = 17, 109 IDMAC_ADC_2 = 18, 110 IDMAC_ADC_3 = 19, 111 IDMAC_ADC_4 = 20, 112 IDMAC_ADC_5 = 21, 113 IDMAC_ADC_6 = 22, 114 IDMAC_ADC_7 = 23, 115 IDMAC_PF_0 = 24, 116 IDMAC_PF_1 = 25, 117 IDMAC_PF_2 = 26, 118 IDMAC_PF_3 = 27, 119 IDMAC_PF_4 = 28, 120 IDMAC_PF_5 = 29, 121 IDMAC_PF_6 = 30, 122 IDMAC_PF_7 = 31, 123 }; 124 125 /* More formats can be copied from the Linux driver if needed */ 126 enum pixel_fmt { 127 /* 2 bytes */ 128 IPU_PIX_FMT_RGB565, 129 IPU_PIX_FMT_RGB666, 130 IPU_PIX_FMT_BGR666, 131 /* 3 bytes */ 132 IPU_PIX_FMT_RGB24, 133 }; 134 135 struct pixel_fmt_cfg { 136 u32 b0; 137 u32 b1; 138 u32 b2; 139 u32 acc; 140 }; 141 142 static struct pixel_fmt_cfg fmt_cfg[] = { 143 [IPU_PIX_FMT_RGB24] = { 144 0x1600AAAA, 0x00E05555, 0x00070000, 3, 145 }, 146 [IPU_PIX_FMT_RGB666] = { 147 0x0005000F, 0x000B000F, 0x0011000F, 1, 148 }, 149 [IPU_PIX_FMT_BGR666] = { 150 0x0011000F, 0x000B000F, 0x0005000F, 1, 151 }, 152 [IPU_PIX_FMT_RGB565] = { 153 0x0004003F, 0x000A000F, 0x000F003F, 1, 154 } 155 }; 156 157 enum ipu_panel { 158 IPU_PANEL_SHARP_TFT, 159 IPU_PANEL_TFT, 160 }; 161 162 /* IPU Common registers */ 163 /* IPU_CONF and its bits already defined in mx31-regs.h */ 164 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) 165 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) 166 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) 167 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) 168 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) 169 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) 170 #define IPU_TASKS_STAT (0x1C + IPU_BASE) 171 #define IPU_IMA_ADDR (0x20 + IPU_BASE) 172 #define IPU_IMA_DATA (0x24 + IPU_BASE) 173 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE) 174 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE) 175 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE) 176 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE) 177 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE) 178 #define IPU_INT_STAT_1 (0x3C + IPU_BASE) 179 #define IPU_INT_STAT_2 (0x40 + IPU_BASE) 180 #define IPU_INT_STAT_3 (0x44 + IPU_BASE) 181 #define IPU_INT_STAT_4 (0x48 + IPU_BASE) 182 #define IPU_INT_STAT_5 (0x4C + IPU_BASE) 183 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) 184 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) 185 #define IPU_BRK_STAT (0x58 + IPU_BASE) 186 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE) 187 188 /* Image Converter Registers */ 189 #define IC_CONF (0x88 + IPU_BASE) 190 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE) 191 #define IC_PRP_VF_RSC (0x90 + IPU_BASE) 192 #define IC_PP_RSC (0x94 + IPU_BASE) 193 #define IC_CMBP_1 (0x98 + IPU_BASE) 194 #define IC_CMBP_2 (0x9C + IPU_BASE) 195 #define PF_CONF (0xA0 + IPU_BASE) 196 #define IDMAC_CONF (0xA4 + IPU_BASE) 197 #define IDMAC_CHA_EN (0xA8 + IPU_BASE) 198 #define IDMAC_CHA_PRI (0xAC + IPU_BASE) 199 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) 200 201 /* Image Converter Register bits */ 202 #define IC_CONF_PRPENC_EN 0x00000001 203 #define IC_CONF_PRPENC_CSC1 0x00000002 204 #define IC_CONF_PRPENC_ROT_EN 0x00000004 205 #define IC_CONF_PRPVF_EN 0x00000100 206 #define IC_CONF_PRPVF_CSC1 0x00000200 207 #define IC_CONF_PRPVF_CSC2 0x00000400 208 #define IC_CONF_PRPVF_CMB 0x00000800 209 #define IC_CONF_PRPVF_ROT_EN 0x00001000 210 #define IC_CONF_PP_EN 0x00010000 211 #define IC_CONF_PP_CSC1 0x00020000 212 #define IC_CONF_PP_CSC2 0x00040000 213 #define IC_CONF_PP_CMB 0x00080000 214 #define IC_CONF_PP_ROT_EN 0x00100000 215 #define IC_CONF_IC_GLB_LOC_A 0x10000000 216 #define IC_CONF_KEY_COLOR_EN 0x20000000 217 #define IC_CONF_RWS_EN 0x40000000 218 #define IC_CONF_CSI_MEM_WR_EN 0x80000000 219 220 /* SDC Registers */ 221 #define SDC_COM_CONF (0xB4 + IPU_BASE) 222 #define SDC_GW_CTRL (0xB8 + IPU_BASE) 223 #define SDC_FG_POS (0xBC + IPU_BASE) 224 #define SDC_BG_POS (0xC0 + IPU_BASE) 225 #define SDC_CUR_POS (0xC4 + IPU_BASE) 226 #define SDC_PWM_CTRL (0xC8 + IPU_BASE) 227 #define SDC_CUR_MAP (0xCC + IPU_BASE) 228 #define SDC_HOR_CONF (0xD0 + IPU_BASE) 229 #define SDC_VER_CONF (0xD4 + IPU_BASE) 230 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) 231 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) 232 233 /* Register bits */ 234 #define SDC_COM_TFT_COLOR 0x00000001UL 235 #define SDC_COM_FG_EN 0x00000010UL 236 #define SDC_COM_GWSEL 0x00000020UL 237 #define SDC_COM_GLB_A 0x00000040UL 238 #define SDC_COM_KEY_COLOR_G 0x00000080UL 239 #define SDC_COM_BG_EN 0x00000200UL 240 #define SDC_COM_SHARP 0x00001000UL 241 242 #define SDC_V_SYNC_WIDTH_L 0x00000001UL 243 244 /* Display Interface registers */ 245 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE) 246 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE) 247 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE) 248 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) 249 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE) 250 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) 251 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) 252 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) 253 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) 254 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) 255 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) 256 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) 257 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) 258 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) 259 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) 260 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) 261 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) 262 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) 263 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) 264 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) 265 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) 266 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) 267 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) 268 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) 269 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) 270 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) 271 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) 272 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) 273 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) 274 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) 275 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) 276 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) 277 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) 278 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) 279 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) 280 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) 281 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) 282 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) 283 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) 284 285 /* DI_DISP_SIG_POL bits */ 286 #define DI_D3_VSYNC_POL (1 << 28) 287 #define DI_D3_HSYNC_POL (1 << 27) 288 #define DI_D3_DRDY_SHARP_POL (1 << 26) 289 #define DI_D3_CLK_POL (1 << 25) 290 #define DI_D3_DATA_POL (1 << 24) 291 292 /* DI_DISP_IF_CONF bits */ 293 #define DI_D3_CLK_IDLE (1 << 26) 294 #define DI_D3_CLK_SEL (1 << 25) 295 #define DI_D3_DATAMSK (1 << 24) 296 297 #define IOMUX_PADNUM_MASK 0x1ff 298 #define IOMUX_GPIONUM_SHIFT 9 299 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) 300 301 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) 302 303 #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) 304 305 enum lcd_pin { 306 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), 307 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), 308 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), 309 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), 310 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), 311 312 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), 313 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), 314 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), 315 316 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), 317 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), 318 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), 319 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), 320 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), 321 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), 322 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), 323 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), 324 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), 325 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), 326 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), 327 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), 328 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), 329 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), 330 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), 331 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), 332 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), 333 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), 334 }; 335 336 struct chan_param_mem_planar { 337 /* Word 0 */ 338 u32 xv:10; 339 u32 yv:10; 340 u32 xb:12; 341 342 u32 yb:12; 343 u32 res1:2; 344 u32 nsb:1; 345 u32 lnpb:6; 346 u32 ubo_l:11; 347 348 u32 ubo_h:15; 349 u32 vbo_l:17; 350 351 u32 vbo_h:9; 352 u32 res2:3; 353 u32 fw:12; 354 u32 fh_l:8; 355 356 u32 fh_h:4; 357 u32 res3:28; 358 359 /* Word 1 */ 360 u32 eba0; 361 362 u32 eba1; 363 364 u32 bpp:3; 365 u32 sl:14; 366 u32 pfs:3; 367 u32 bam:3; 368 u32 res4:2; 369 u32 npb:6; 370 u32 res5:1; 371 372 u32 sat:2; 373 u32 res6:30; 374 } __attribute__ ((packed)); 375 376 struct chan_param_mem_interleaved { 377 /* Word 0 */ 378 u32 xv:10; 379 u32 yv:10; 380 u32 xb:12; 381 382 u32 yb:12; 383 u32 sce:1; 384 u32 res1:1; 385 u32 nsb:1; 386 u32 lnpb:6; 387 u32 sx:10; 388 u32 sy_l:1; 389 390 u32 sy_h:9; 391 u32 ns:10; 392 u32 sm:10; 393 u32 sdx_l:3; 394 395 u32 sdx_h:2; 396 u32 sdy:5; 397 u32 sdrx:1; 398 u32 sdry:1; 399 u32 sdr1:1; 400 u32 res2:2; 401 u32 fw:12; 402 u32 fh_l:8; 403 404 u32 fh_h:4; 405 u32 res3:28; 406 407 /* Word 1 */ 408 u32 eba0; 409 410 u32 eba1; 411 412 u32 bpp:3; 413 u32 sl:14; 414 u32 pfs:3; 415 u32 bam:3; 416 u32 res4:2; 417 u32 npb:6; 418 u32 res5:1; 419 420 u32 sat:2; 421 u32 scc:1; 422 u32 ofs0:5; 423 u32 ofs1:5; 424 u32 ofs2:5; 425 u32 ofs3:5; 426 u32 wid0:3; 427 u32 wid1:3; 428 u32 wid2:3; 429 430 u32 wid3:3; 431 u32 dec_sel:1; 432 u32 res6:28; 433 } __attribute__ ((packed)); 434 435 union chan_param_mem { 436 struct chan_param_mem_planar pp; 437 struct chan_param_mem_interleaved ip; 438 }; 439 440 static inline u32 reg_read(unsigned long reg) 441 { 442 return __REG(reg); 443 } 444 445 static inline void reg_write(u32 value, unsigned long reg) 446 { 447 __REG(reg) = value; 448 } 449 450 /* 451 * sdc_init_panel() - initialize a synchronous LCD panel. 452 * @width: width of panel in pixels. 453 * @height: height of panel in pixels. 454 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. 455 * @return: 0 on success or negative error code on failure. 456 */ 457 static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt) 458 { 459 u32 reg; 460 uint32_t old_conf; 461 462 /* Init panel size and blanking periods */ 463 reg = ((H_SYNC_WIDTH - 1) << 26) | 464 ((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16); 465 reg_write(reg, SDC_HOR_CONF); 466 467 reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L | 468 ((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16); 469 reg_write(reg, SDC_VER_CONF); 470 471 switch (PANEL_TYPE) { 472 case IPU_PANEL_SHARP_TFT: 473 reg_write(0x00FD0102L, SDC_SHARP_CONF_1); 474 reg_write(0x00F500F4L, SDC_SHARP_CONF_2); 475 reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); 476 break; 477 case IPU_PANEL_TFT: 478 reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF); 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 /* Init clocking */ 485 486 /* 487 * Calculate divider: fractional part is 4 bits so simply multiple by 488 * 2^4 to get fractional part, as long as we stay under ~250MHz and on 489 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz 490 */ 491 492 reg_write((((IF_CLK_DIV / 8) - 1) << 22) | 493 IF_CLK_DIV, DI_DISP3_TIME_CONF); 494 495 /* DI settings */ 496 old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF; 497 reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF); 498 499 old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF; 500 reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL); 501 502 reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP); 503 reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP); 504 reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP); 505 reg_write(reg_read(DI_DISP_ACC_CC) | 506 ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC); 507 508 return 0; 509 } 510 511 static void ipu_ch_param_set_size(union chan_param_mem *params, 512 uint32_t pixel_fmt, uint16_t width, 513 uint16_t height, uint16_t stride) 514 { 515 params->pp.fw = width - 1; 516 params->pp.fh_l = height - 1; 517 params->pp.fh_h = (height - 1) >> 8; 518 params->pp.sl = stride - 1; 519 520 /* See above, for further formats see the Linux driver */ 521 switch (pixel_fmt) { 522 case IPU_PIX_FMT_RGB565: 523 params->ip.bpp = 2; 524 params->ip.pfs = 4; 525 params->ip.npb = 7; 526 params->ip.sat = 2; /* SAT = 32-bit access */ 527 params->ip.ofs0 = 0; /* Red bit offset */ 528 params->ip.ofs1 = 5; /* Green bit offset */ 529 params->ip.ofs2 = 11; /* Blue bit offset */ 530 params->ip.ofs3 = 16; /* Alpha bit offset */ 531 params->ip.wid0 = 4; /* Red bit width - 1 */ 532 params->ip.wid1 = 5; /* Green bit width - 1 */ 533 params->ip.wid2 = 4; /* Blue bit width - 1 */ 534 break; 535 case IPU_PIX_FMT_RGB24: 536 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ 537 params->ip.pfs = 4; 538 params->ip.npb = 7; 539 params->ip.sat = 2; /* SAT = 32-bit access */ 540 params->ip.ofs0 = 16; /* Red bit offset */ 541 params->ip.ofs1 = 8; /* Green bit offset */ 542 params->ip.ofs2 = 0; /* Blue bit offset */ 543 params->ip.ofs3 = 24; /* Alpha bit offset */ 544 params->ip.wid0 = 7; /* Red bit width - 1 */ 545 params->ip.wid1 = 7; /* Green bit width - 1 */ 546 params->ip.wid2 = 7; /* Blue bit width - 1 */ 547 break; 548 default: 549 break; 550 } 551 552 params->pp.nsb = 1; 553 } 554 555 static void ipu_ch_param_set_buffer(union chan_param_mem *params, 556 void *buf0, void *buf1) 557 { 558 params->pp.eba0 = (u32)buf0; 559 params->pp.eba1 = (u32)buf1; 560 } 561 562 static void ipu_write_param_mem(uint32_t addr, uint32_t *data, 563 uint32_t num_words) 564 { 565 for (; num_words > 0; num_words--) { 566 reg_write(addr, IPU_IMA_ADDR); 567 reg_write(*data++, IPU_IMA_DATA); 568 addr++; 569 if ((addr & 0x7) == 5) { 570 addr &= ~0x7; /* set to word 0 */ 571 addr += 8; /* increment to next row */ 572 } 573 } 574 } 575 576 static uint32_t bpp_to_pixfmt(int bpp) 577 { 578 switch (bpp) { 579 case 16: 580 return IPU_PIX_FMT_RGB565; 581 default: 582 return 0; 583 } 584 } 585 586 static uint32_t dma_param_addr(enum ipu_channel channel) 587 { 588 /* Channel Parameter Memory */ 589 return 0x10000 | (channel << 4); 590 } 591 592 static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) 593 { 594 union chan_param_mem params = {}; 595 uint32_t reg; 596 uint32_t stride_bytes; 597 598 stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3; 599 600 /* Build parameter memory data for DMA channel */ 601 ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(BIT_PER_PIXEL), 602 XRES, YRES, stride_bytes); 603 ipu_ch_param_set_buffer(¶ms, fbmem, NULL); 604 params.pp.bam = 0; 605 /* Some channels (rotation) have restriction on burst length */ 606 607 switch (channel) { 608 case IDMAC_SDC_0: 609 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ 610 params.pp.npb = 16 - 1; 611 break; 612 default: 613 break; 614 } 615 616 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); 617 618 /* Disable double-buffering */ 619 reg = reg_read(IPU_CHA_DB_MODE_SEL); 620 reg &= ~(1UL << channel); 621 reg_write(reg, IPU_CHA_DB_MODE_SEL); 622 } 623 624 static void ipu_channel_set_priority(enum ipu_channel channel, 625 int prio) 626 { 627 u32 reg = reg_read(IDMAC_CHA_PRI); 628 629 if (prio) 630 reg |= 1UL << channel; 631 else 632 reg &= ~(1UL << channel); 633 634 reg_write(reg, IDMAC_CHA_PRI); 635 } 636 637 /* 638 * ipu_enable_channel() - enable an IPU channel. 639 * @channel: channel ID. 640 * @return: 0 on success or negative error code on failure. 641 */ 642 static int ipu_enable_channel(enum ipu_channel channel) 643 { 644 uint32_t reg; 645 646 /* Reset to buffer 0 */ 647 reg_write(1UL << channel, IPU_CHA_CUR_BUF); 648 649 switch (channel) { 650 case IDMAC_SDC_0: 651 ipu_channel_set_priority(channel, 1); 652 break; 653 default: 654 break; 655 } 656 657 reg = reg_read(IDMAC_CHA_EN); 658 reg_write(reg | (1UL << channel), IDMAC_CHA_EN); 659 660 return 0; 661 } 662 663 static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) 664 { 665 uint32_t reg; 666 667 reg = reg_read(IPU_CHA_BUF0_RDY); 668 if (reg & (1UL << channel)) 669 return -EACCES; 670 671 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ 672 reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); 673 reg_write((u32)buf, IPU_IMA_DATA); 674 675 return 0; 676 } 677 678 static int idmac_tx_submit(enum ipu_channel channel, void *buf) 679 { 680 int ret; 681 682 ipu_init_channel_buffer(channel, buf); 683 684 685 /* ipu_idmac.c::ipu_submit_channel_buffers() */ 686 ret = ipu_update_channel_buffer(channel, buf); 687 if (ret < 0) 688 return ret; 689 690 /* ipu_idmac.c::ipu_select_buffer() */ 691 /* Mark buffer 0 as ready. */ 692 reg_write(1UL << channel, IPU_CHA_BUF0_RDY); 693 694 695 ret = ipu_enable_channel(channel); 696 return ret; 697 } 698 699 static void sdc_enable_channel(void *fbmem) 700 { 701 int ret; 702 u32 reg; 703 704 ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); 705 706 /* mx3fb.c::sdc_fb_init() */ 707 if (ret >= 0) { 708 reg = reg_read(SDC_COM_CONF); 709 reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF); 710 } 711 712 /* 713 * Attention! Without this msleep the channel keeps generating 714 * interrupts. Next sdc_set_brightness() is going to be called 715 * from mx3fb_blank(). 716 */ 717 msleep(2); 718 } 719 720 /* 721 * mx3fb_set_par() - set framebuffer parameters and change the operating mode. 722 * @return: 0 on success or negative error code on failure. 723 */ 724 static int mx3fb_set_par(void) 725 { 726 int ret; 727 728 ret = sdc_init_panel(XRES, YRES, PIXEL_FMT); 729 if (ret < 0) 730 return ret; 731 732 reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS); 733 734 return 0; 735 } 736 737 /* References in this function refer to respective Linux kernel sources */ 738 void lcd_enable(void) 739 { 740 u32 reg; 741 742 /* pcm037.c::mxc_board_init() */ 743 744 /* Display Interface #3 */ 745 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); 746 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); 747 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); 748 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); 749 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); 750 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); 751 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); 752 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); 753 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); 754 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); 755 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); 756 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); 757 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); 758 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); 759 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); 760 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); 761 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); 762 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); 763 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); 764 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); 765 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); 766 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); 767 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); 768 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); 769 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); 770 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); 771 772 773 /* ipu_idmac.c::ipu_probe() */ 774 775 /* Start the clock */ 776 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); 777 778 779 /* ipu_idmac.c::ipu_idmac_init() */ 780 781 /* Service request counter to maximum - shouldn't be needed */ 782 reg_write(0x00000070, IDMAC_CONF); 783 784 785 /* ipu_idmac.c::ipu_init_channel() */ 786 787 /* Enable IPU sub modules */ 788 reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; 789 reg_write(reg, IPU_CONF); 790 791 792 /* mx3fb.c::init_fb_chan() */ 793 794 /* set Display Interface clock period */ 795 reg_write(0x00100010L, DI_HSP_CLK_PER); 796 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ 797 798 799 /* mx3fb.c::sdc_set_brightness() */ 800 801 /* This might be board-specific */ 802 reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL); 803 804 805 /* mx3fb.c::sdc_set_global_alpha() */ 806 807 /* Use global - not per-pixel - Alpha-blending */ 808 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; 809 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); 810 811 reg = reg_read(SDC_COM_CONF); 812 reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF); 813 814 815 /* mx3fb.c::sdc_set_color_key() */ 816 817 /* Disable colour-keying for background */ 818 reg = reg_read(SDC_COM_CONF) & 819 ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); 820 reg_write(reg, SDC_COM_CONF); 821 822 823 mx3fb_set_par(); 824 825 sdc_enable_channel(lcd_base); 826 827 /* 828 * Linux driver calls sdc_set_brightness() here again, 829 * once is enough for us 830 */ 831 } 832 833 void lcd_ctrl_init(void *lcdbase) 834 { 835 u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8; 836 /* 837 * We rely on lcdbase being a physical address, i.e., either MMU off, 838 * or 1-to-1 mapping. Might want to add some virt2phys here. 839 */ 840 if (!lcdbase) 841 return; 842 843 memset(lcdbase, 0, mem_len); 844 } 845 846 ulong calc_fbsize(void) 847 { 848 return ((panel_info.vl_col * panel_info.vl_row * 849 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; 850 } 851 852 int overwrite_console(void) 853 { 854 /* Keep stdout / stderr on serial, our LCD is for splashscreen only */ 855 return 1; 856 } 857