1 /* 2 * Copyright (C) 2009 3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <lcd.h> 25 #include <asm/arch/mx31.h> 26 #include <asm/arch/mx31-regs.h> 27 #include <asm/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 void *lcd_base; /* Start of framebuffer memory */ 32 void *lcd_console_address; /* Start of console buffer */ 33 34 int lcd_line_length; 35 int lcd_color_fg; 36 int lcd_color_bg; 37 38 short console_col; 39 short console_row; 40 41 void lcd_initcolregs(void) 42 { 43 } 44 45 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 46 { 47 } 48 49 void lcd_disable(void) 50 { 51 } 52 53 void lcd_panel_disable(void) 54 { 55 } 56 57 #define msleep(a) udelay(a * 1000) 58 59 #if defined(CONFIG_DISPLAY_VBEST_VGG322403) 60 #define XRES 320 61 #define YRES 240 62 #define PANEL_TYPE IPU_PANEL_TFT 63 #define PIXEL_CLK 156000 64 #define PIXEL_FMT IPU_PIX_FMT_RGB666 65 #define H_START_WIDTH 20 /* left_margin */ 66 #define H_SYNC_WIDTH 30 /* hsync_len */ 67 #define H_END_WIDTH (38 + 30) /* right_margin + hsync_len */ 68 #define V_START_WIDTH 7 /* upper_margin */ 69 #define V_SYNC_WIDTH 3 /* vsync_len */ 70 #define V_END_WIDTH (26 + 3) /* lower_margin + vsync_len */ 71 #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) 72 #define IF_CONF 0 73 #define IF_CLK_DIV 0x175 74 #elif defined(CONFIG_DISPLAY_COM57H5M10XRC) 75 #define XRES 640 76 #define YRES 480 77 #define PANEL_TYPE IPU_PANEL_TFT 78 #define PIXEL_CLK 40000 79 #define PIXEL_FMT IPU_PIX_FMT_RGB666 80 #define H_START_WIDTH 120 /* left_margin */ 81 #define H_SYNC_WIDTH 30 /* hsync_len */ 82 #define H_END_WIDTH (10 + 30) /* right_margin + hsync_len */ 83 #define V_START_WIDTH 35 /* upper_margin */ 84 #define V_SYNC_WIDTH 3 /* vsync_len */ 85 #define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */ 86 #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) 87 #define IF_CONF 0 88 #define IF_CLK_DIV 0x175 89 #else 90 #define XRES 240 91 #define YRES 320 92 #define PANEL_TYPE IPU_PANEL_TFT 93 #define PIXEL_CLK 185925 94 #define PIXEL_FMT IPU_PIX_FMT_RGB666 95 #define H_START_WIDTH 9 /* left_margin */ 96 #define H_SYNC_WIDTH 1 /* hsync_len */ 97 #define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ 98 #define V_START_WIDTH 7 /* upper_margin */ 99 #define V_SYNC_WIDTH 1 /* vsync_len */ 100 #define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ 101 #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) 102 #define IF_CONF 0 103 #define IF_CLK_DIV 0x175 104 #endif 105 106 #define LCD_COLOR_IPU LCD_COLOR16 107 108 static ushort colormap[256]; 109 110 vidinfo_t panel_info = { 111 .vl_col = XRES, 112 .vl_row = YRES, 113 .vl_bpix = LCD_COLOR_IPU, 114 .cmap = colormap, 115 }; 116 117 #define BIT_PER_PIXEL NBITS(LCD_COLOR_IPU) 118 119 /* IPU DMA Controller channel definitions. */ 120 enum ipu_channel { 121 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ 122 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ 123 IDMAC_ADC_0 = 1, 124 IDMAC_IC_2 = 2, 125 IDMAC_ADC_1 = 2, 126 IDMAC_IC_3 = 3, 127 IDMAC_IC_4 = 4, 128 IDMAC_IC_5 = 5, 129 IDMAC_IC_6 = 6, 130 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ 131 IDMAC_IC_8 = 8, 132 IDMAC_IC_9 = 9, 133 IDMAC_IC_10 = 10, 134 IDMAC_IC_11 = 11, 135 IDMAC_IC_12 = 12, 136 IDMAC_IC_13 = 13, 137 IDMAC_SDC_0 = 14, /* Background synchronous display data */ 138 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ 139 IDMAC_SDC_2 = 16, 140 IDMAC_SDC_3 = 17, 141 IDMAC_ADC_2 = 18, 142 IDMAC_ADC_3 = 19, 143 IDMAC_ADC_4 = 20, 144 IDMAC_ADC_5 = 21, 145 IDMAC_ADC_6 = 22, 146 IDMAC_ADC_7 = 23, 147 IDMAC_PF_0 = 24, 148 IDMAC_PF_1 = 25, 149 IDMAC_PF_2 = 26, 150 IDMAC_PF_3 = 27, 151 IDMAC_PF_4 = 28, 152 IDMAC_PF_5 = 29, 153 IDMAC_PF_6 = 30, 154 IDMAC_PF_7 = 31, 155 }; 156 157 /* More formats can be copied from the Linux driver if needed */ 158 enum pixel_fmt { 159 /* 2 bytes */ 160 IPU_PIX_FMT_RGB565, 161 IPU_PIX_FMT_RGB666, 162 IPU_PIX_FMT_BGR666, 163 /* 3 bytes */ 164 IPU_PIX_FMT_RGB24, 165 }; 166 167 struct pixel_fmt_cfg { 168 u32 b0; 169 u32 b1; 170 u32 b2; 171 u32 acc; 172 }; 173 174 static struct pixel_fmt_cfg fmt_cfg[] = { 175 [IPU_PIX_FMT_RGB24] = { 176 0x1600AAAA, 0x00E05555, 0x00070000, 3, 177 }, 178 [IPU_PIX_FMT_RGB666] = { 179 0x0005000F, 0x000B000F, 0x0011000F, 1, 180 }, 181 [IPU_PIX_FMT_BGR666] = { 182 0x0011000F, 0x000B000F, 0x0005000F, 1, 183 }, 184 [IPU_PIX_FMT_RGB565] = { 185 0x0004003F, 0x000A000F, 0x000F003F, 1, 186 } 187 }; 188 189 enum ipu_panel { 190 IPU_PANEL_SHARP_TFT, 191 IPU_PANEL_TFT, 192 }; 193 194 /* IPU Common registers */ 195 /* IPU_CONF and its bits already defined in mx31-regs.h */ 196 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) 197 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) 198 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) 199 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) 200 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) 201 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) 202 #define IPU_TASKS_STAT (0x1C + IPU_BASE) 203 #define IPU_IMA_ADDR (0x20 + IPU_BASE) 204 #define IPU_IMA_DATA (0x24 + IPU_BASE) 205 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE) 206 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE) 207 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE) 208 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE) 209 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE) 210 #define IPU_INT_STAT_1 (0x3C + IPU_BASE) 211 #define IPU_INT_STAT_2 (0x40 + IPU_BASE) 212 #define IPU_INT_STAT_3 (0x44 + IPU_BASE) 213 #define IPU_INT_STAT_4 (0x48 + IPU_BASE) 214 #define IPU_INT_STAT_5 (0x4C + IPU_BASE) 215 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) 216 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) 217 #define IPU_BRK_STAT (0x58 + IPU_BASE) 218 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE) 219 220 /* Image Converter Registers */ 221 #define IC_CONF (0x88 + IPU_BASE) 222 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE) 223 #define IC_PRP_VF_RSC (0x90 + IPU_BASE) 224 #define IC_PP_RSC (0x94 + IPU_BASE) 225 #define IC_CMBP_1 (0x98 + IPU_BASE) 226 #define IC_CMBP_2 (0x9C + IPU_BASE) 227 #define PF_CONF (0xA0 + IPU_BASE) 228 #define IDMAC_CONF (0xA4 + IPU_BASE) 229 #define IDMAC_CHA_EN (0xA8 + IPU_BASE) 230 #define IDMAC_CHA_PRI (0xAC + IPU_BASE) 231 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) 232 233 /* Image Converter Register bits */ 234 #define IC_CONF_PRPENC_EN 0x00000001 235 #define IC_CONF_PRPENC_CSC1 0x00000002 236 #define IC_CONF_PRPENC_ROT_EN 0x00000004 237 #define IC_CONF_PRPVF_EN 0x00000100 238 #define IC_CONF_PRPVF_CSC1 0x00000200 239 #define IC_CONF_PRPVF_CSC2 0x00000400 240 #define IC_CONF_PRPVF_CMB 0x00000800 241 #define IC_CONF_PRPVF_ROT_EN 0x00001000 242 #define IC_CONF_PP_EN 0x00010000 243 #define IC_CONF_PP_CSC1 0x00020000 244 #define IC_CONF_PP_CSC2 0x00040000 245 #define IC_CONF_PP_CMB 0x00080000 246 #define IC_CONF_PP_ROT_EN 0x00100000 247 #define IC_CONF_IC_GLB_LOC_A 0x10000000 248 #define IC_CONF_KEY_COLOR_EN 0x20000000 249 #define IC_CONF_RWS_EN 0x40000000 250 #define IC_CONF_CSI_MEM_WR_EN 0x80000000 251 252 /* SDC Registers */ 253 #define SDC_COM_CONF (0xB4 + IPU_BASE) 254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) 255 #define SDC_FG_POS (0xBC + IPU_BASE) 256 #define SDC_BG_POS (0xC0 + IPU_BASE) 257 #define SDC_CUR_POS (0xC4 + IPU_BASE) 258 #define SDC_PWM_CTRL (0xC8 + IPU_BASE) 259 #define SDC_CUR_MAP (0xCC + IPU_BASE) 260 #define SDC_HOR_CONF (0xD0 + IPU_BASE) 261 #define SDC_VER_CONF (0xD4 + IPU_BASE) 262 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) 263 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) 264 265 /* Register bits */ 266 #define SDC_COM_TFT_COLOR 0x00000001UL 267 #define SDC_COM_FG_EN 0x00000010UL 268 #define SDC_COM_GWSEL 0x00000020UL 269 #define SDC_COM_GLB_A 0x00000040UL 270 #define SDC_COM_KEY_COLOR_G 0x00000080UL 271 #define SDC_COM_BG_EN 0x00000200UL 272 #define SDC_COM_SHARP 0x00001000UL 273 274 #define SDC_V_SYNC_WIDTH_L 0x00000001UL 275 276 /* Display Interface registers */ 277 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE) 278 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE) 279 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE) 280 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) 281 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE) 282 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) 283 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) 284 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) 285 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) 286 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) 287 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) 288 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) 289 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) 290 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) 291 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) 292 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) 293 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) 294 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) 295 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) 296 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) 297 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) 298 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) 299 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) 300 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) 301 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) 302 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) 303 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) 304 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) 305 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) 306 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) 307 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) 308 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) 309 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) 310 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) 311 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) 312 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) 313 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) 314 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) 315 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) 316 317 /* DI_DISP_SIG_POL bits */ 318 #define DI_D3_VSYNC_POL (1 << 28) 319 #define DI_D3_HSYNC_POL (1 << 27) 320 #define DI_D3_DRDY_SHARP_POL (1 << 26) 321 #define DI_D3_CLK_POL (1 << 25) 322 #define DI_D3_DATA_POL (1 << 24) 323 324 /* DI_DISP_IF_CONF bits */ 325 #define DI_D3_CLK_IDLE (1 << 26) 326 #define DI_D3_CLK_SEL (1 << 25) 327 #define DI_D3_DATAMSK (1 << 24) 328 329 #define IOMUX_PADNUM_MASK 0x1ff 330 #define IOMUX_GPIONUM_SHIFT 9 331 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) 332 333 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) 334 335 #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) 336 337 enum lcd_pin { 338 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), 339 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), 340 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), 341 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), 342 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), 343 344 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), 345 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), 346 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), 347 348 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), 349 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), 350 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), 351 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), 352 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), 353 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), 354 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), 355 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), 356 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), 357 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), 358 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), 359 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), 360 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), 361 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), 362 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), 363 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), 364 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), 365 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), 366 }; 367 368 struct chan_param_mem_planar { 369 /* Word 0 */ 370 u32 xv:10; 371 u32 yv:10; 372 u32 xb:12; 373 374 u32 yb:12; 375 u32 res1:2; 376 u32 nsb:1; 377 u32 lnpb:6; 378 u32 ubo_l:11; 379 380 u32 ubo_h:15; 381 u32 vbo_l:17; 382 383 u32 vbo_h:9; 384 u32 res2:3; 385 u32 fw:12; 386 u32 fh_l:8; 387 388 u32 fh_h:4; 389 u32 res3:28; 390 391 /* Word 1 */ 392 u32 eba0; 393 394 u32 eba1; 395 396 u32 bpp:3; 397 u32 sl:14; 398 u32 pfs:3; 399 u32 bam:3; 400 u32 res4:2; 401 u32 npb:6; 402 u32 res5:1; 403 404 u32 sat:2; 405 u32 res6:30; 406 } __attribute__ ((packed)); 407 408 struct chan_param_mem_interleaved { 409 /* Word 0 */ 410 u32 xv:10; 411 u32 yv:10; 412 u32 xb:12; 413 414 u32 yb:12; 415 u32 sce:1; 416 u32 res1:1; 417 u32 nsb:1; 418 u32 lnpb:6; 419 u32 sx:10; 420 u32 sy_l:1; 421 422 u32 sy_h:9; 423 u32 ns:10; 424 u32 sm:10; 425 u32 sdx_l:3; 426 427 u32 sdx_h:2; 428 u32 sdy:5; 429 u32 sdrx:1; 430 u32 sdry:1; 431 u32 sdr1:1; 432 u32 res2:2; 433 u32 fw:12; 434 u32 fh_l:8; 435 436 u32 fh_h:4; 437 u32 res3:28; 438 439 /* Word 1 */ 440 u32 eba0; 441 442 u32 eba1; 443 444 u32 bpp:3; 445 u32 sl:14; 446 u32 pfs:3; 447 u32 bam:3; 448 u32 res4:2; 449 u32 npb:6; 450 u32 res5:1; 451 452 u32 sat:2; 453 u32 scc:1; 454 u32 ofs0:5; 455 u32 ofs1:5; 456 u32 ofs2:5; 457 u32 ofs3:5; 458 u32 wid0:3; 459 u32 wid1:3; 460 u32 wid2:3; 461 462 u32 wid3:3; 463 u32 dec_sel:1; 464 u32 res6:28; 465 } __attribute__ ((packed)); 466 467 union chan_param_mem { 468 struct chan_param_mem_planar pp; 469 struct chan_param_mem_interleaved ip; 470 }; 471 472 static inline u32 reg_read(unsigned long reg) 473 { 474 return __REG(reg); 475 } 476 477 static inline void reg_write(u32 value, unsigned long reg) 478 { 479 __REG(reg) = value; 480 } 481 482 /* 483 * sdc_init_panel() - initialize a synchronous LCD panel. 484 * @width: width of panel in pixels. 485 * @height: height of panel in pixels. 486 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. 487 * @return: 0 on success or negative error code on failure. 488 */ 489 static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt) 490 { 491 u32 reg; 492 uint32_t old_conf; 493 494 /* Init panel size and blanking periods */ 495 reg = ((H_SYNC_WIDTH - 1) << 26) | 496 ((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16); 497 reg_write(reg, SDC_HOR_CONF); 498 499 reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L | 500 ((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16); 501 reg_write(reg, SDC_VER_CONF); 502 503 switch (PANEL_TYPE) { 504 case IPU_PANEL_SHARP_TFT: 505 reg_write(0x00FD0102L, SDC_SHARP_CONF_1); 506 reg_write(0x00F500F4L, SDC_SHARP_CONF_2); 507 reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); 508 break; 509 case IPU_PANEL_TFT: 510 reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF); 511 break; 512 default: 513 return -EINVAL; 514 } 515 516 /* Init clocking */ 517 518 /* 519 * Calculate divider: fractional part is 4 bits so simply multiple by 520 * 2^4 to get fractional part, as long as we stay under ~250MHz and on 521 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz 522 */ 523 524 reg_write((((IF_CLK_DIV / 8) - 1) << 22) | 525 IF_CLK_DIV, DI_DISP3_TIME_CONF); 526 527 /* DI settings */ 528 old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF; 529 reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF); 530 531 old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF; 532 reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL); 533 534 reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP); 535 reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP); 536 reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP); 537 reg_write(reg_read(DI_DISP_ACC_CC) | 538 ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC); 539 540 return 0; 541 } 542 543 static void ipu_ch_param_set_size(union chan_param_mem *params, 544 uint32_t pixel_fmt, uint16_t width, 545 uint16_t height, uint16_t stride) 546 { 547 params->pp.fw = width - 1; 548 params->pp.fh_l = height - 1; 549 params->pp.fh_h = (height - 1) >> 8; 550 params->pp.sl = stride - 1; 551 552 /* See above, for further formats see the Linux driver */ 553 switch (pixel_fmt) { 554 case IPU_PIX_FMT_RGB565: 555 params->ip.bpp = 2; 556 params->ip.pfs = 4; 557 params->ip.npb = 7; 558 params->ip.sat = 2; /* SAT = 32-bit access */ 559 params->ip.ofs0 = 0; /* Red bit offset */ 560 params->ip.ofs1 = 5; /* Green bit offset */ 561 params->ip.ofs2 = 11; /* Blue bit offset */ 562 params->ip.ofs3 = 16; /* Alpha bit offset */ 563 params->ip.wid0 = 4; /* Red bit width - 1 */ 564 params->ip.wid1 = 5; /* Green bit width - 1 */ 565 params->ip.wid2 = 4; /* Blue bit width - 1 */ 566 break; 567 case IPU_PIX_FMT_RGB24: 568 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ 569 params->ip.pfs = 4; 570 params->ip.npb = 7; 571 params->ip.sat = 2; /* SAT = 32-bit access */ 572 params->ip.ofs0 = 16; /* Red bit offset */ 573 params->ip.ofs1 = 8; /* Green bit offset */ 574 params->ip.ofs2 = 0; /* Blue bit offset */ 575 params->ip.ofs3 = 24; /* Alpha bit offset */ 576 params->ip.wid0 = 7; /* Red bit width - 1 */ 577 params->ip.wid1 = 7; /* Green bit width - 1 */ 578 params->ip.wid2 = 7; /* Blue bit width - 1 */ 579 break; 580 default: 581 break; 582 } 583 584 params->pp.nsb = 1; 585 } 586 587 static void ipu_ch_param_set_buffer(union chan_param_mem *params, 588 void *buf0, void *buf1) 589 { 590 params->pp.eba0 = (u32)buf0; 591 params->pp.eba1 = (u32)buf1; 592 } 593 594 static void ipu_write_param_mem(uint32_t addr, uint32_t *data, 595 uint32_t num_words) 596 { 597 for (; num_words > 0; num_words--) { 598 reg_write(addr, IPU_IMA_ADDR); 599 reg_write(*data++, IPU_IMA_DATA); 600 addr++; 601 if ((addr & 0x7) == 5) { 602 addr &= ~0x7; /* set to word 0 */ 603 addr += 8; /* increment to next row */ 604 } 605 } 606 } 607 608 static uint32_t bpp_to_pixfmt(int bpp) 609 { 610 switch (bpp) { 611 case 16: 612 return IPU_PIX_FMT_RGB565; 613 default: 614 return 0; 615 } 616 } 617 618 static uint32_t dma_param_addr(enum ipu_channel channel) 619 { 620 /* Channel Parameter Memory */ 621 return 0x10000 | (channel << 4); 622 } 623 624 static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) 625 { 626 union chan_param_mem params = {}; 627 uint32_t reg; 628 uint32_t stride_bytes; 629 630 stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3; 631 632 /* Build parameter memory data for DMA channel */ 633 ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(BIT_PER_PIXEL), 634 XRES, YRES, stride_bytes); 635 ipu_ch_param_set_buffer(¶ms, fbmem, NULL); 636 params.pp.bam = 0; 637 /* Some channels (rotation) have restriction on burst length */ 638 639 switch (channel) { 640 case IDMAC_SDC_0: 641 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ 642 params.pp.npb = 16 - 1; 643 break; 644 default: 645 break; 646 } 647 648 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); 649 650 /* Disable double-buffering */ 651 reg = reg_read(IPU_CHA_DB_MODE_SEL); 652 reg &= ~(1UL << channel); 653 reg_write(reg, IPU_CHA_DB_MODE_SEL); 654 } 655 656 static void ipu_channel_set_priority(enum ipu_channel channel, 657 int prio) 658 { 659 u32 reg = reg_read(IDMAC_CHA_PRI); 660 661 if (prio) 662 reg |= 1UL << channel; 663 else 664 reg &= ~(1UL << channel); 665 666 reg_write(reg, IDMAC_CHA_PRI); 667 } 668 669 /* 670 * ipu_enable_channel() - enable an IPU channel. 671 * @channel: channel ID. 672 * @return: 0 on success or negative error code on failure. 673 */ 674 static int ipu_enable_channel(enum ipu_channel channel) 675 { 676 uint32_t reg; 677 678 /* Reset to buffer 0 */ 679 reg_write(1UL << channel, IPU_CHA_CUR_BUF); 680 681 switch (channel) { 682 case IDMAC_SDC_0: 683 ipu_channel_set_priority(channel, 1); 684 break; 685 default: 686 break; 687 } 688 689 reg = reg_read(IDMAC_CHA_EN); 690 reg_write(reg | (1UL << channel), IDMAC_CHA_EN); 691 692 return 0; 693 } 694 695 static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) 696 { 697 uint32_t reg; 698 699 reg = reg_read(IPU_CHA_BUF0_RDY); 700 if (reg & (1UL << channel)) 701 return -EACCES; 702 703 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ 704 reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); 705 reg_write((u32)buf, IPU_IMA_DATA); 706 707 return 0; 708 } 709 710 static int idmac_tx_submit(enum ipu_channel channel, void *buf) 711 { 712 int ret; 713 714 ipu_init_channel_buffer(channel, buf); 715 716 717 /* ipu_idmac.c::ipu_submit_channel_buffers() */ 718 ret = ipu_update_channel_buffer(channel, buf); 719 if (ret < 0) 720 return ret; 721 722 /* ipu_idmac.c::ipu_select_buffer() */ 723 /* Mark buffer 0 as ready. */ 724 reg_write(1UL << channel, IPU_CHA_BUF0_RDY); 725 726 727 ret = ipu_enable_channel(channel); 728 return ret; 729 } 730 731 static void sdc_enable_channel(void *fbmem) 732 { 733 int ret; 734 u32 reg; 735 736 ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); 737 738 /* mx3fb.c::sdc_fb_init() */ 739 if (ret >= 0) { 740 reg = reg_read(SDC_COM_CONF); 741 reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF); 742 } 743 744 /* 745 * Attention! Without this msleep the channel keeps generating 746 * interrupts. Next sdc_set_brightness() is going to be called 747 * from mx3fb_blank(). 748 */ 749 msleep(2); 750 } 751 752 /* 753 * mx3fb_set_par() - set framebuffer parameters and change the operating mode. 754 * @return: 0 on success or negative error code on failure. 755 */ 756 static int mx3fb_set_par(void) 757 { 758 int ret; 759 760 ret = sdc_init_panel(XRES, YRES, PIXEL_FMT); 761 if (ret < 0) 762 return ret; 763 764 reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS); 765 766 return 0; 767 } 768 769 /* References in this function refer to respective Linux kernel sources */ 770 void lcd_enable(void) 771 { 772 u32 reg; 773 774 /* pcm037.c::mxc_board_init() */ 775 776 /* Display Interface #3 */ 777 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); 778 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); 779 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); 780 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); 781 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); 782 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); 783 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); 784 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); 785 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); 786 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); 787 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); 788 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); 789 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); 790 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); 791 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); 792 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); 793 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); 794 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); 795 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); 796 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); 797 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); 798 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); 799 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); 800 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); 801 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); 802 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); 803 804 805 /* ipu_idmac.c::ipu_probe() */ 806 807 /* Start the clock */ 808 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); 809 810 811 /* ipu_idmac.c::ipu_idmac_init() */ 812 813 /* Service request counter to maximum - shouldn't be needed */ 814 reg_write(0x00000070, IDMAC_CONF); 815 816 817 /* ipu_idmac.c::ipu_init_channel() */ 818 819 /* Enable IPU sub modules */ 820 reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; 821 reg_write(reg, IPU_CONF); 822 823 824 /* mx3fb.c::init_fb_chan() */ 825 826 /* set Display Interface clock period */ 827 reg_write(0x00100010L, DI_HSP_CLK_PER); 828 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ 829 830 831 /* mx3fb.c::sdc_set_brightness() */ 832 833 /* This might be board-specific */ 834 reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL); 835 836 837 /* mx3fb.c::sdc_set_global_alpha() */ 838 839 /* Use global - not per-pixel - Alpha-blending */ 840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; 841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); 842 843 reg = reg_read(SDC_COM_CONF); 844 reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF); 845 846 847 /* mx3fb.c::sdc_set_color_key() */ 848 849 /* Disable colour-keying for background */ 850 reg = reg_read(SDC_COM_CONF) & 851 ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); 852 reg_write(reg, SDC_COM_CONF); 853 854 855 mx3fb_set_par(); 856 857 sdc_enable_channel(lcd_base); 858 859 /* 860 * Linux driver calls sdc_set_brightness() here again, 861 * once is enough for us 862 */ 863 } 864 865 void lcd_ctrl_init(void *lcdbase) 866 { 867 u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8; 868 /* 869 * We rely on lcdbase being a physical address, i.e., either MMU off, 870 * or 1-to-1 mapping. Might want to add some virt2phys here. 871 */ 872 if (!lcdbase) 873 return; 874 875 memset(lcdbase, 0, mem_len); 876 } 877 878 ulong calc_fbsize(void) 879 { 880 return ((panel_info.vl_col * panel_info.vl_row * 881 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; 882 } 883 884 int overwrite_console(void) 885 { 886 /* Keep stdout / stderr on serial, our LCD is for splashscreen only */ 887 return 1; 888 } 889